-------------------------------------------------------------
-- N to 1 bit Mux
-- Author       : B. Ryan Northcott
-- Student ID   : 252494
-- Date         : Mar 2, 2001
-- File Name    : MuxN_1.vhd
-- Architecture : Behavioral
-- Description  : 
--
-- Acknowledgements:
-------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MuxN_1 is
    generic
	(
		N : positive := 20;	-- Number of input lines
		C : positive := 5	-- Number of control lines
	);
    port
	(
		Input   : in std_logic_vector( N-1 downto 0 );
		Sel     : in std_logic_vector( C-1 downto 0 );
		Output  : out std_logic
	);
end MuxN_1;

-- Behavioral Implementation of the Mux
architecture behavioral of MuxN_1 is
begin
	process(Input,Sel)
	begin
		if Sel = 0 then
			Output <= Input(0);
		elsif Sel = 1 then
			Output <= Input(1);
		elsif Sel = 2 then
			Output <= Input(2);
		elsif Sel = 3 then
			Output <= Input(3);
		elsif Sel = 4 then
			Output <= Input(4);
		elsif Sel = 5 then
			Output <= Input(5);
		elsif Sel = 6 then
			Output <= Input(6);
		elsif Sel = 7 then
			Output <= Input(7);
		elsif Sel = 8 then
			Output <= Input(8);
		elsif Sel = 9 then
			Output <= Input(9);
		elsif Sel = 10 then
			Output <= Input(10);
		elsif Sel = 11 then
			Output <= Input(11);
		elsif Sel = 12 then
			Output <= Input(12);
		elsif Sel = 13 then
			Output <= Input(13);
		elsif Sel = 14 then
			Output <= Input(14);
		elsif Sel = 15 then
			Output <= Input(15);
		elsif Sel = 16 then
			Output <= Input(16);
		elsif Sel = 17 then
			Output <= Input(17);
		elsif Sel = 18 then
			Output <= Input(18);
		elsif Sel = 19 then
			Output <= Input(19);
		else
			Output <= '0';
		end if;
	end process;
end behavioral;