----------------------------------------------------------
-- regKeyData
-- Author   : Gautam Karnik
-- Date     : March 30, 2001
-- Filename : regKeyData.vhd
-- Architecture : Behavioral
-- Description  : This entity is a D-Flipflop 
--                register used to map to the
--                keyEncode module.
----------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
library work;
use work.CDMA_pkg.all;

entity regKeyData is
  	  generic ( datawidth : positive := 3 );
      port ( enable : in std_logic;
	         clock  : in std_logic;
		     clearn : in std_logic;
		     clr  	: in std_logic;
		     d_usr1_en   : in std_logic;
		     d_usr1_data : in std_logic_vector ( datawidth-1 downto 0);
		     d_usr2_en   : in std_logic;
		     d_usr2_data : in std_logic_vector ( datawidth-1 downto 0);
		     q_usr1_en   : out std_logic;
		     q_usr1_data : out std_logic_vector ( datawidth-1 downto 0);
		     q_usr2_en   : out std_logic;
		     q_usr2_data : out std_logic_vector ( datawidth-1 downto 0)
           );
end entity regKeyData;

architecture behavioral of regKeyData is

signal q_usr1_en_temp, q_usr2_en_temp : std_logic;
signal q_usr1_data_temp, q_usr2_data_temp : std_logic_vector ( datawidth-1 downto 0 );

begin
flipflop : process is 
begin
 wait until rising_edge(clock);
 if ( clearn = '0' ) then
    q_usr1_en_temp   <= '0';
    q_usr1_data_temp <= (others => '0');
    q_usr2_en_temp   <= '0';
    q_usr2_data_temp <= (others => '0');
 elsif ( clr = '1' ) then
    q_usr1_en_temp   <= '0';
    q_usr1_data_temp <= (others => '0');
    q_usr2_en_temp   <= '0';
    q_usr2_data_temp <= (others => '0');
 elsif ( enable = '1' ) then
    q_usr1_en_temp   <= d_usr1_en;
    q_usr1_data_temp <= d_usr1_data;
    q_usr2_en_temp   <= d_usr2_en;
    q_usr2_data_temp <= d_usr2_data;
 else
    q_usr1_en_temp   <= q_usr1_en_temp;
    q_usr1_data_temp <= q_usr1_data_temp;
    q_usr2_en_temp   <= q_usr2_en_temp;
    q_usr2_data_temp <= q_usr2_data_temp;
 end if;
end process flipflop;

q_usr1_en   <= q_usr1_en_temp;
q_usr1_data <= q_usr1_data_temp;
q_usr2_en   <= q_usr2_en_temp;
q_usr2_data <= q_usr2_data_temp;


end behavioral;