------------------------------------------------------------------------------
--Author: Xiaofei Vivien Dong
--Course: ee552
--Project: CDMA Based communication systems
------------------------------------------------------------------------------
--musr_transmitter receives parallel frame data from frame_builder, spreads
-- the data onto 8-bit spreading code, attach 8-bit synchronization code at
-- before the frame data and transmit at 25MHz/4 bps.

-- Total logic cells used:                         54/1152   (  4%)
-----------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_transmitter is
	port (
    	resetn, clock : in  std_logic;

		parallel_to_serial_load, parallel_to_serial_clk_en : in std_logic;
		spreading_load, spreading_clk_en : in std_logic;
		sync_code_load, sync_code_clk_en : in std_logic;

    	frame_in     : in  std_logic_vector( frame_length -1 downto 0);

    	Tx           : out std_logic
	);
end musr_transmitter;

architecture rtl of musr_transmitter is


-- all the enable signals come from the clk_master; 
    signal dff_en, scramble_en, sync_en : std_logic;
    signal scramble_load, sync_load : std_logic;
    signal dffout_en : std_logic;
    signal frame_bit : std_logic;
    signal ones : std_logic;
    signal ps_en : std_logic;
    signal ps_load : std_logic;
    signal data_temp1, data_temp2 : std_logic_vector( frame_length downto 0);
  
begin  -- rtl

	ones <= '1';

	ps_load 		<= parallel_to_serial_load;
	ps_en 			<= parallel_to_serial_clk_en;
	scramble_load 	<= spreading_load;
	scramble_en 	<= spreading_clk_en;
	sync_load 		<= sync_code_load;
	sync_en 		<= sync_code_clk_en;

-- change parallel data in to serials at 25Mhz/32 bps;  every bit is hold for
-- 8 main clock periods spreading;
-- spreaded data will not output till the synchronization code has been
-- transmitted first

	data_temp1 <= frame_in & '0';

Parallel_To_Serials : shiftreg
    generic map (register_width => 13)
    port map (
	    resetn           => resetn,
    	clk              => clock,
	    enable           => ps_en,
    	load             => ps_load,
	    d                => data_temp1,
    	q                => data_temp2,
	    shiftout         => frame_bit
	);

-- encoder spreads frame data using the scamble_code and attaches the
-- synchronization code;
  
encode: encoder2 
	port map (
		clock 			=> clock,
		resetn 			=> resetn,
		frame_in 		=> frame_bit,
		sync_en 		=> sync_en,
		load_sync 		=> sync_load,
		spreading_en	=> scramble_en,
		load_scramble 	=> scramble_load,
		dffout_en 		=> dffout_en,
		transmit_out 	=> Tx
	);

	-- the output of the transmitted is not controled at this stage;
	dffout_en <= '1';


end rtl;