-- Total logic cells used:                         63/1152   (  5%)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_synchronizer is
	generic (code_width : positive := 32);-- sample at 4 times the transmitted bps
	port (
		resetn, clock	: in  std_logic;
		device_en		: in  std_logic;
		Rx				: in  std_logic;
		frame_bit		: out std_logic;
		bit_ready		: out std_logic  --bit_ready is active for only
	);
end musr_synchronizer;

architecture behavioural of musr_synchronizer is

	signal adden2 : std_logic_vector(31 downto 0);

	signal bit_in, flag : std_logic;
	signal ones,zeros : std_logic ;
	signal adden1 :std_logic_vector(code_width-1 downto 0);
	signal bit_ready_internal : std_logic;
	signal distance : std_logic_vector(5 downto 0);
	signal weight_vec : std_logic_vector(31 downto 0);

begin  -- behavioural

  ones <= '1';
  zeros <= '0';
  adden2 <= x"0fff00f0";

serial2parallel: s2preg
	generic map (WIDTH => code_width)
	port map (
		clock     => clock,
		resetn    => resetn,
		enable    => device_en,	-- always enabled unless changed by root
		bitin     => Rx,
		frameout  => adden1
	);

	weight_vec <= adden1 xnor adden2;

	-- four stages of pipelines;
measure : pipelinedmeter 
	port map (
		resetn        => resetn,
		clock         => clock,
		weight_vector => weight_vec,
		distance      => distance
	);

decision: process
	begin

		wait until rising_edge(clock);
		if resetn = '0' then
			flag <= '0';
		elsif distance = X"20" then
			flag <= '1';
		else
			flag <= '0';
		end if;

		bit_ready <= flag;

	end process;

	frame_bit <= adden1(5); -- the 5th bits of register is outputed.
							-- the number of "5" is determined by the timing relation.
  
end behavioural;