----------------------------------------------------------
-- Mobile User Master Clock Controller
-- Author   : Ai Hua
-- Date     : March 30, 2001
-- Filename : musr_reciever_clk_master.vhd
-- Architecture : Behavioral
-- Description  : This entity is the core controller
--                which control all the timing realtion
--                of recieving a frame
-- Total logic cells used: 33/1152   (  2%)
----------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_reciever_clk_master is
    generic (num_clk_en : positive := 7);
    port ( 
		resetn, sys_clk : in std_logic;

		frame_recieved : in std_logic;

		channel_ready : in std_logic;

		-- tell the keypad component that new key_in can be handled again.
		-- it 's used to close present process in all the other component.
		work_period_over : out std_logic; 

		despreading_input_clk_en : out std_logic;
		despreading_output_clk_en : out std_logic;

		frame_analyzer_input_clk_en : out std_logic;
		frame_analyzer_frame_clk_en : out std_logic;
		frame_analyzer_output_clk_en : out std_logic;

		display_input_en : out std_logic;

		busy : out std_logic

    );
end musr_reciever_clk_master;

architecture behavioral of musr_reciever_clk_master is

signal temp_clk_en, temp_load : std_logic;
signal temp_d, temp_q : std_logic_vector(clock_counter_datawidth-1 downto 0);

signal temp_despreading_input_clk_en : std_logic;
signal temp_despreading_output_clk_en : std_logic;
signal temp_despreading_begin : std_logic;
signal temp_despreading_over : std_logic;

signal temp_frame_analyzer_input_clk_en : std_logic;
signal temp_frame_analyzer_frame_clk_en : std_logic;
signal temp_frame_analyzer_output_clk_en : std_logic;
signal temp_frame_analyzer_output_clk_en1 : std_logic;

signal temp_display_input_en : std_logic;
signal temp_display_input_en1 : std_logic;

signal temp_work_period_over : std_logic; 

signal tmp_in, tmp_out : std_logic_vector(num_clk_en-1 downto 0 );
signal not_busy, temp_busy : std_logic;

type working_state is (waiting, before_working, working, after_working);
signal state : working_state;

type despreading_state is (waiting, despreading);
signal Is_despreading : despreading_state;


begin

	temp_d <= (others => '0');
	temp_clk_en <= '1';
	temp_load <= frame_recieved; -- coming from synchronizer
	
clock_counter : work_period_clocker 
    generic map (datawidth => clock_counter_datawidth)
	PORT map (
		clk 	=> sys_clk,
		resetn 	=> resetn,
		clk_en 	=> temp_clk_en,
		load 	=> frame_recieved,
		d 		=> temp_d,
		q 		=> temp_q
	);


	with temp_q select
		temp_despreading_begin <= '1' when "0000000000",
							 	  '0' when others;
	with temp_q select
		temp_despreading_over <= '1' when "0110000000",
							 	 '0' when others;

	with temp_q select
		temp_frame_analyzer_input_clk_en <= '1' when "0000100000",
								 	 	   '1' when "0001000000",
										   '1' when "0001100000",
										   '1' when "0010000000",
										   '1' when "0010100000",
										   '1' when "0011000000",
										   '1' when "0011100000",
										   '1' when "0100000000",
										   '1' when "0100100000",
										   '1' when "0101000000",
										   '1' when "0101100000",
										   '1' when "0110000000",
										   '0' when others;

	-- work_period_over is set to valid at 416th 25M clock period for 3 periods.
	with temp_q select
		temp_frame_analyzer_frame_clk_en <= '1' when "0110000001",
								 		   '0' when others;

	with temp_q select
		temp_frame_analyzer_output_clk_en1 <= '1' when "0110000010",
								 		   '0' when others;
	temp_frame_analyzer_output_clk_en <= temp_frame_analyzer_output_clk_en1 
											and channel_ready;

	with temp_q select
		temp_display_input_en1 <= '1' when "0110000011",
								'0' when others;
	temp_display_input_en <= temp_display_input_en1 and channel_ready; 


	with temp_q select
		temp_work_period_over <= '1' when "0110000011",
							 	'0' when others;

Check_despreading_state : process
	begin
		wait until sys_clk'event and sys_clk = '1';
		if resetn = '0' then
			Is_despreading <= waiting;
		else
			case Is_despreading is 
				when waiting =>
					if temp_despreading_begin = '1' then
						Is_despreading <= despreading;
					else
						Is_despreading <= waiting;
					end if;
				when despreading =>
					if temp_despreading_over = '1' then
						Is_despreading <= waiting;
					else
						Is_despreading <= despreading;
					end if;
			end case;
		end if;
	end process Check_despreading_state;

	with Is_despreading select
		temp_despreading_input_clk_en 
			<= (not temp_q(1)) and temp_q(0) when despreading,
				'0' when others;

	with Is_despreading select
		temp_despreading_output_clk_en 
			<= temp_q(4) and temp_q(3) and temp_q(2) and temp_q(1) and 
				temp_q(0) when despreading,
				'0' when others;


Is_System_Busy : process (sys_clk, resetn)
	begin
		wait until sys_clk'event and sys_clk = '1';
		if resetn = '0' then
			state <= waiting;
		else
			case state is 
				when waiting =>
					if temp_load = '0' then
						state <= before_working;
					else
						state <= waiting;
					end if;
				when before_working =>
					if temp_load = '0' then
						state <= before_working;
					else
						state <= working;
					end if;
				when working =>
					if temp_work_period_over = '0' then
						state <= working;
					else
						state <= after_working;
					end if;
				when after_working =>
					if temp_load = '0' then
						state <= before_working;
					else
						state <= waiting;
					end if;
			end case;
		end if;
	end process Is_System_Busy;
			
	with state select
		temp_busy <= '1' when working,
					 '1' when after_working,
					 '0' when others;
	busy <= temp_busy;

	not_busy <= not temp_busy;

registerout : myflipflops
	Generic map (datawidth => num_clk_en)
	port map ( 
		clk => sys_clk,
		clearn => temp_busy,
		enable => temp_clk_en,
		d => tmp_in,
		q => tmp_out
	);

	tmp_in <= temp_despreading_input_clk_en & temp_despreading_output_clk_en & 
				temp_frame_analyzer_input_clk_en & temp_frame_analyzer_frame_clk_en & 
				temp_frame_analyzer_output_clk_en & temp_display_input_en &
				temp_work_period_over;


	despreading_input_clk_en 		<= tmp_out(6);
	despreading_output_clk_en 		<= tmp_out(5);
	frame_analyzer_input_clk_en 	<= tmp_out(4);
	frame_analyzer_frame_clk_en 	<= tmp_out(3);
	frame_analyzer_output_clk_en 	<= tmp_out(2);
	display_input_en				<= tmp_out(1);
	work_period_over				<= tmp_out(0);
	

end behavioral;