----------------------------------------------------------
-- musr_keypad
-- Author   : Gautam Karnik
-- Date     : March 30, 2001
-- Filename : musr_keypad.vhd
-- Architecture : Structural
-- Description  : This module serves as the interface
--                module between the keypad and the rest
--                of the back-end system.  
----------------------------------------------------------

--------------------------------------------------------------------
-- Total logic cells used:                        102/1152   (  8%)
--------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_keypad is
	generic(datawidth : positive := 3);
	port(
    	resetn, clock, clk_en : in std_logic;
		usr1_en, usr2_en : in std_logic;
		keypad_col : out std_logic_vector(3 downto 0);
		keypad_row : in std_logic_vector(3 downto 0);
		channel_ready : in std_logic;
		usr1_online, usr2_online : out std_logic;
		usr1_data : out std_logic_vector(datawidth-1 downto 0);
		usr2_data : out std_logic_vector(datawidth-1 downto 0);
		key_valid : out std_logic
	);
end musr_keypad;

architecture structural of musr_keypad is

signal high : std_logic;
signal reg4_row : std_logic_vector (3 downto 0);
signal detector_sense : std_logic;
signal decoder_row : std_logic_vector ( 3 downto 0);
signal decoder_col : std_logic_vector ( 3 downto 0);
signal driver_col  : std_logic_vector ( 3 downto 0);
signal debouncer_keyPressed, debouncer_keyPressed_inv : std_logic;
signal validator_keyValid : std_logic;
signal encoder_usr1_data, encoder_usr2_data : std_logic_vector ( 2 downto 0);
signal temp_usr1_online, temp_usr2_online : std_logic;
signal both_usr_offline : std_logic;

begin

	high <= '1';
	both_usr_offline <= not (usr1_en or usr2_en);

detector : component keySense
	generic map ( datawidth => 4 )
	port map (
		resetn 	=> resetn,
		clock 	=> clock,
		row 	=> keypad_row,
		sense 	=> detector_sense
	);

	debouncer_keyPressed_inv <= not debouncer_keyPressed;

decoder : component keyDecode
	generic map ( datawidth => 4 )
	port map ( 
		resetn 	=> resetn,
		clock 	=> clock,
		clear 	=> both_usr_offline,
		rowIn 	=> keypad_row,
		sense 	=> debouncer_keyPressed_inv,
		rowOut 	=> decoder_row
	);

driver : component keyDriver
	generic map ( datawidth => 4)
	port map ( 
		resetn 		=> resetn,
		clock 		=> clock,
		enable 		=> detector_sense,
		keyPressed 	=> debouncer_keyPressed,
		driveCol 	=> driver_col,
		Col 		=> decoder_col
	);

debouncer : component keyDebounce
	port map ( 
		resetn 		=> resetn,
		clock 		=> clock,
		sense 		=> detector_sense,
		keyPressed 	=> debouncer_keyPressed
	);

validator : component keyValidator
	port map ( 
		resetn 			=> resetn,
		clock 			=> clock,
		channel_status 	=> channel_ready,
		usr1_online 	=> temp_usr1_online,
		usr2_online 	=> temp_usr2_online,
		keyPressed   	=> debouncer_keyPressed,
		keyValid     	=> validator_keyValid
	);

encoder : component keyEncode
	port map ( 
		resetn 		=> resetn,
		clock 		=> clock,
		row   		=> decoder_row,
		col   		=> decoder_col,
		usr1_data 	=> encoder_usr1_data,
		usr2_data 	=> encoder_usr2_data	
	);

reg1 : component reg1bit
	port map ( 
		enable	=> high,
		clock  	=> clock,
		clearn 	=> resetn,
		d      	=> validator_keyValid,
		q      	=> key_valid
	);

	temp_usr1_online <= not (decoder_row(0) and decoder_row(1)) and usr1_en;
	temp_usr2_online <= not (decoder_row(2) and decoder_row(3)) and usr2_en;

regData : component regKeyData
	generic map ( datawidth => 3 )
	port map ( 
		enable 		=> clk_en,
		clock  		=> clock,
		clearn		=> resetn,
		clr 	  	=> both_usr_offline,
		d_usr1_en 	=> temp_usr1_online,
		d_usr1_data	=> encoder_usr1_data,
		d_usr2_en 	=> temp_usr2_online,
		d_usr2_data => encoder_usr2_data,
		q_usr1_en 	=> usr1_online,
		q_usr1_data => usr1_data,
		q_usr2_en 	=> usr2_online,
		q_usr2_data => usr2_data
	);

	keypad_col <= driver_col;

end structural;