---------------------------------------------------------------------
-- Mobile User Frame Analyzer
-- Author   : Ai Hua
-- Date     : March 30, 2001
-- Filename : musr_frame_analyzer.vhd
-- Architecture : Behavioral
-- Description  : 
--
-- Get the received frame from despreading module.
-- If it's a ACK frame, then
--    1. Inform frame_builder.
-- If it's a response frame, then give the data to right usr
-- display module

-- Total logic cells used:                         37/1152   (  3%)

---------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_frame_analyzer is
	generic ( 
		datawidth 		: positive := 8;
		frame_length 	: positive := 12
	);
	port (
		resetn, clock 	: in std_logic;
		input_clk_en, frame_clk_en, output_clk_en : in std_logic;

        channel_ready 	: in std_logic;
        bitstream_in 	: in std_logic;

		ACK_back : out std_logic;
		usr_data : out std_logic_vector(datawidth-1 downto 0)
	);
end entity musr_frame_analyzer;



architecture a of musr_frame_analyzer is

	signal temp_q 				: std_logic_vector(frame_length-1 downto 0);
	signal temp_frame_in 		: std_logic_vector(frame_length-1 downto 0);
	signal temp_ACK_back 		: std_logic;
	signal temp_output_clk_en 	: std_logic;
	signal temp_usr_data 		: std_logic_vector(datawidth-1 downto 0);
	signal Is_ACK_frame 		: std_logic;
	signal type_of_frame 		: std_logic_vector(3 downto 0);

	TYPE ACK_response_state IS (waiting , not_recieved, recieved);
	SIGNAL ACK_state 			: ACK_response_state;

begin

Serial_To_Paralle : process (clock)
	begin
		wait until clock'event and clock = '1';
		if resetn = '0' then
			temp_q <= (others => '0');
		else
			if input_clk_en = '1' then
				temp_q <= temp_q(frame_length-2 downto 0) & bitstream_in;
			else
				temp_q <= temp_q;
			end if;
		end if;
	end process Serial_To_Paralle;


To_Recieve_frame : myflipflops
	generic map (datawidth => frame_length)
    port map ( 
		clk 	=> clock,
		enable 	=> frame_clk_en,
        clearn 	=> resetn,

        d 		=> temp_q, 
        q 		=> temp_frame_in
    );


	-- when we find the present frame is a ACK frame, we will have no interests in the data.
	-- so disable the output_clk_en with ACK_back.
	temp_output_clk_en <= output_clk_en and channel_ready;

sent_to_LCD : myflipflops
	generic map (datawidth => datawidth)
    port map ( 
		clk 	=> clock,
		enable 	=> temp_output_clk_en, -- active high
        clearn 	=> resetn,   -- active low resetn

        d 		=> temp_usr_data, 
        q 		=> usr_data
    );

	temp_usr_data <= temp_frame_in(datawidth-1 downto 0);
	type_of_frame <= temp_frame_in(frame_length-1 downto datawidth);

	with type_of_frame select
		Is_ACK_frame  <= 	'1' when "1100",
--		Is_ACK_frame  <= 	'1' when "0011", -- for feedback test.
							'0' when others;

Check_ACK_state : process (clock)	
	begin
		wait until clock'event and clock = '1';
		if resetn = '0' then
			ACK_state <= waiting;
			temp_ACK_back <= '0';
		else
			case ACK_state is
				when waiting =>

					if Is_ACK_frame = '0' then
						ACK_state <= not_recieved;
					else
						ACK_state <= waiting;
					end if;
					
				when not_recieved =>

					temp_ACK_back <= '0';
					if Is_ACK_frame = '1' then
						ACK_state <= recieved;
					else
						ACK_state <= not_recieved;
					end if;

				when recieved =>

					temp_ACK_back <= '1';
					ACK_state <= waiting;

				when others =>

					ACK_state <= waiting;

			end case;
		end if;
	end process Check_ACK_state;

	ACK_back <= temp_ACK_back;


end a;