----------------------------
-- Mobile User LCD Control
-- Author   : Gautam Karnik, Ai Hua
-- Date     : March 30, 2001
-- Filename : base_DIGIT_control.vhd
-- Architecture : Behavioral
-- Description  : This module is used to interface with the DIGIT
--                display on the UP1 Board for the specified user in
--                the base station.
-- Acknowledgements: based on LCD driver code provided by 
--                   Author : David Li, Eric Cheun, 
--                            Felicia Cheng, Wilson Kwan
--                   Date   : 2000 winter
---------------------------------------------------------------------
-- Total logic cells used:                        166/1152   ( 14%)


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity musr_LCD_control is
	generic( 
		width 		: positive := 8;
		datawidth 	: positive := 3
	);
	port( 
		resetn, clock, clk_en : in std_logic;

		-- indicates when mobile user is on-line
		usr1_online : in std_logic;
		usr2_online : in std_logic;
  	    usr1_data 	: in std_logic_vector(datawidth-1 downto 0);
		usr2_data 	: in std_logic_vector(datawidth-1 downto 0);
		lcd1_select, lcd1_rw, lcd1_enable : out std_logic;
        lcd1_data 	: out std_logic_vector(width-1 downto 0);
		lcd2_select, lcd2_rw, lcd2_enable : out std_logic;
        lcd2_data 	: out std_logic_vector(width-1 downto 0)
	);
end musr_LCD_control;

architecture structural of musr_LCD_control is

	signal slowclock : std_logic;
	signal display_en : std_logic;
	signal display_lcd1, display_lcd2 : std_logic;
	signal slowdown_en : std_logic;

	type en_state is (enabled, disabled); 
	signal clk_en_state, slowclock_state : en_state;

begin

counter1: counter
	generic map (counter_size=>4000)-- slow the clock down
	port map(
		clock		=> clock,
		resetn		=> resetn,
		outclock	=> slowclock
	);

detect_clk_en : process (clock) is
	begin
		wait until clock'event and clock = '0';
		if resetn = '0' then 
			clk_en_state <= disabled;
		else
			case clk_en_state is
				when enabled =>
					if clk_en = '0' then
						clk_en_state <= disabled;
					end if;

				when disabled =>
					if clk_en = '1' then
						clk_en_state <= enabled;
					end if;

				when others =>
					clk_en_state <= enabled;

			end case;
		end if;
	end process detect_clk_en;

detect_slowclock_state : process (clock) is
	begin
		wait until clock'event and clock = '0';
		if resetn = '0' then 
			slowclock_state <= disabled;
		else
			case slowclock_state is
				when enabled =>
					if slowclock = '0' then
						slowclock_state <= disabled;
					end if;

				when disabled =>
					if slowclock = '1' then
						slowclock_state <= enabled;
					end if;

				when others =>
					slowclock_state <= enabled;
			end case;
		end if;
	end process detect_slowclock_state;

enable_control : process (clock) is 
	begin
		wait until clock'event and clock = '1';
		if resetn = '0' then
			slowdown_en <= '0';
		elsif clk_en_state = enabled then
			slowdown_en <= '1';
		elsif slowclock_state = enabled then
			slowdown_en <= '0';
		end if;
	end process enable_control;

	display_lcd1 <= slowdown_en and usr1_online;
	display_lcd2 <= slowdown_en and usr2_online;

lcd1_driver: lcddriver 
	port map(
		clock  		=> clock,
		clk_en		=> slowclock,
		resetn  	=> resetn,
		enable 		=> display_lcd1,
		lcd_data   	=> lcd1_data,
		lcd_rw     	=> lcd1_rw,
		lcd_enable 	=> lcd1_enable,
		lcd_select 	=> lcd1_select,
		message    	=> usr1_data
	);

lcd2_driver: lcddriver 
	port map(
		clock  		=> clock,
		clk_en		=> slowclock,
		resetn  	=> resetn,
		enable 		=> display_lcd2,
		lcd_data   	=> lcd2_data,
		lcd_rw     	=> lcd2_rw,
		lcd_enable 	=> lcd2_enable,
		lcd_select 	=> lcd2_select,
		message    	=> usr2_data
	);

end structural;