---------------------------------------------------------- -- keyDriver -- Author : Gautam Karnik -- Date : March 30, 2001 -- Filename : keyDriver.vhd -- Architecture : Behavioral -- Description : This entity drives the output column -- lines to the keypad sequentially in order -- to determine which key has been pressed. -- The driver stops driving when the input -- lines go back high. ---------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.CDMA_pkg.all; entity keyDriver is generic ( datawidth : positive := 4 ); port ( resetn : in std_logic; clock : in std_logic; enable : in std_logic; keyPressed : in std_logic; driveCol : out std_logic_vector(datawidth-1 downto 0); Col : out std_logic_vector(datawidth-1 downto 0) ); end entity keyDriver; architecture behavioral of keyDriver is signal detecting : std_logic; signal high : std_logic; signal tmp_Col : std_logic_vector(datawidth-1 downto 0); signal tmp_driveCol : std_logic_vector(datawidth-1 downto 0); begin high <= '1'; Key_is_valid : process (clock) is begin wait until clock'event and clock = '1'; if (keyPressed = '1' and enable = '0') then detecting <= '1'; elsif (enable = '1') then detecting <= '0'; end if; end process Key_is_valid; drive : process (clock, resetn) is variable count : std_logic_vector ( 2 downto 0); begin wait until rising_edge ( clock ); if ( resetn = '0' ) then count := (others => '0'); tmp_driveCol <= (others => '0'); else if (detecting = '1' and enable = '0') then count := count + '1'; CASE count IS WHEN "000" => tmp_driveCol <= "0000"; WHEN "001" => tmp_driveCol <= "0001"; WHEN "010" => tmp_driveCol <= "0010"; WHEN "011" => tmp_driveCol <= "0100"; WHEN "100" => tmp_driveCol <= "1000"; count := "000"; WHEN OTHERS => tmp_driveCol<= "0000"; END CASE; else count := (others => '0'); tmp_driveCol <= "0000"; end if; end if; end process drive; -- For the sake of timing relation. delay_cols_information1 : myflipflops generic map (datawidth => 4) port map ( clk => clock, enable => high, clearn => resetn, d => tmp_driveCol, q => tmp_Col ); register_cols : myflipflops generic map (datawidth => 4) port map ( clk => clock, enable => detecting, -- active high clearn => resetn, -- active low reset d => tmp_Col, q => Col ); driveCol <= tmp_driveCol; end behavioral;