-----------------------------------------------------------------------------
-- Author: Xiaofei Vivien Dong
-- Course: ee552
-- Project: CDMA based communication systems
-------------------------------------------------------------------------------
-- encoder.vhd spread every input data bit onto 8 bits of scramble
-- code; the enable signal comes from upper layer.  Add 8 bits sync
-- code. suppose the minimum clock period (i.e. the maximum clock
-- frequnce) is decided by clock signal, we keep this frequence and
-- generate enable signals that corresponds to our requirement of bit
-- rate. suppose the input bitstream has a bit rate of 1/4/8/clock;
-- the output has a frequency that is 8 times of the input bitstream.
-- the output bit rate is 1/4/clock; resetn is active low
-- total logic cells used 30/1152
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity encoder2 is
	generic (code_length : positive := 8);
	port (
    	clock, resetn	: in  std_logic;

	    frame_in		: in std_logic;		-- at bps 25MHz/32;

		sync_en			: in std_logic;
    	load_sync		: in std_logic;

	    spreading_en	: in std_logic;
		load_scramble	: in std_logic;

    	dffout_en		: in  std_logic;	--clk_enable 25MHz/4;
	    transmit_out	: out std_logic
	);										--output has bit
											--rate 25MHz/4;
end encoder2;  

architecture uplink of encoder2 is
  
--constant synccode : std_logic_vector(code_length-1 downto 0) := "01110010";
--constant scramblecode : std_logic_vector(code_length-1 downto 0) := "11110000";

	signal load_code, bit_in, bit_out : std_logic;
	signal shift_scramble, shift_sync: std_logic;
	signal synccode,scramblecode : std_logic_vector(code_length-1 downto 0);
	signal temp1, temp2 : std_logic_vector(code_length-1 downto 0);             
	signal scrambling_bit : std_logic;

begin  -- unlink


	synccode <= "01110010";
	scramblecode <= "11110000";

sync_code : shiftreg 
	generic map (register_width => code_length)
	port map (
		resetn 		=> resetn,
		clk   		=> clock,               
		enable  	=> sync_en,
		d     		=> synccode,
		load    	=> load_sync,
		q       	=> temp1,
		shiftout  	=> shift_sync
	);

 -- purpose: generate sync_code_out enable at 25Mhz/4 bps; enable maintein high for 40ns*32, then low for 12*32*40ns;
 -- type   : combinational
 -- inputs : frame_ready
 -- outputs: sync_en

  
spreading: shiftreg 
	generic map (register_width => code_length)
	port map (
		clk			=> clock,			-- clock_en should be sys_clock/4 in freq
		enable		=> spreading_en,	--should always be '1' ?????? NO!!!!!
		resetn		=> resetn,
		load		=> load_scramble,
		d			=> scramblecode,
		q			=> temp2,
		shiftout	=> shift_scramble
	);
    
	scrambling_bit <= frame_in xor shift_scramble;
	bit_out <= shift_sync or scrambling_bit ;

dff_out : dff_en 
	port map (
		resetn  => resetn,
		clock  => clock,
		enable => dffout_en,
		d      => bit_out,
		q      => transmit_out
	);


end uplink;