-- this is an imcomplete adder. for n bits of input, regular adder should have
-- 2^n possible inputs of adden1, but we have only half of the possible inputs,
-- so the n bit incomplete adder is similar to an n-1 bit adder.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.CDMA_pkg.all;

entity adderinc is
	generic (width : positive := 2);
	port (
		adden1 : in  std_logic_vector(width-1 downto 0);
		adden2 : in  std_logic_vector(width-1 downto 0);
		sum    : out std_logic_vector(width downto 0)
	);
end adderinc;

architecture behavioural of adderinc is

	signal lowersum : std_logic_vector(width -1 downto 0);
	signal zeros : std_logic_vector(width-1 downto 0);
	signal sel : std_logic_vector(1 downto 0);
	signal adden1_internal, adden2_internal : std_logic_vector(width-1 downto 0);
begin  -- behavioural

	zeros <= (others =>'0');
	sel <= adden1(width-1) & adden2(width-1);

selects: process
	begin  -- process
		case sel is
			when "00" => sum <= '0' & lowersum ;
			when "01" => sum <= "01" & adden1(width-2 downto 0);
			when "10" => sum <= "01" & adden2(width-2 downto 0);
			when "11" => sum <= '1' & zeros;
			when others => null;
		end case;
	end process;

	adden1_internal <= '0' & adden1(width-2 downto 0);
	adden2_internal <= '0' & adden2(width-2 downto 0);

	lowersum <= adden1_internal + adden2_internal;

end behavioural;