-----------------------------------------------------------------
-- vector_to_7seg.vhd
-- Christopher Kowalski
-- 
-- Converts a 4-bit vector to be displayed on a 7-segment LED.
-- The value of the scan code pressed is the output.
-- 
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity vector_to_7seg is
	port(vector		: in std_logic_vector(3 downto 0);
		reset,
		clock		: in std_logic;
		done 		: in std_logic;
		seg1 		: out std_logic_vector(6 downto 0);
		seg2		: out std_logic_vector(6 downto 0));
end vector_to_7seg;

architecture behavioural of vector_to_7seg is

	-- declare internal signals
		
begin

		
	convert : process (clock) is

	-- process variable
	variable count:natural range 0 to 2;
	
	begin
		if rising_edge(clock) then
		if reset = '1' then
			seg1 <= (others => '0');
			seg2 <= (others => '0');
		elsif done = '1' then  -- a load signal

		case vector is
			
		when "0000" =>			-- x77 NumLock
			seg1 <= "1111000";
			seg2 <= "1111000";

		when "0001" =>			-- x6C 7
			seg1 <= "0000010";
			seg2 <= "1000110";

		when "0010" =>			-- x75 8
			seg1 <= "1111000";
			seg2 <= "0010010";

		when "0011" =>			-- x7D 9
			seg1 <= "1111000";
			seg2 <= "0100001";

		when "0100" =>			-- x6B 4
			seg1 <= "0000010";
			seg2 <= "0000011";

		when "0101" =>			-- x73 5
			seg1 <= "1111000";
			seg2 <= "0110000";

		when "0110" =>			-- x74 6
			seg1 <= "1111000";
			seg2 <= "0011001";

		when "0111" =>			-- x69 1
			seg1 <= "0000010";
			seg2 <= "0011000";

		when "1000" =>			-- x72 2
			seg1 <= "1111000";
			seg2 <= "0100100";

		when "1001" =>			-- x7A 3
			seg1 <= "1111000";
			seg2 <= "0001000";

		when "1010" =>			-- x70 0
			seg1 <= "1111000";
			seg2 <= "1000000";

		when "1011" =>			-- x71 .
			seg1 <= "1111000";
			seg2 <= "1111001";

		when "1100" =>			-- x79 +
			seg1 <= "1111000";
			seg2 <= "0011000";

		when others =>
			seg1 <= "1000000";
			seg2 <= "1000000";

		end case;
		end if;		
		end if;

	end process convert;
end behavioural;