-----------------------------------------------------------------
-- serialout.vhd
-- Christopher Kowalski
--
-- RS-232 Serial Port Out
--
-- The following VHDL code makes a RS-232 output port
-- It is  set up for:
-- Word Length:	7bits
-- Parity:	odd
-- Stop bits:	1
-- Data Rate:	9600 baud
--
-- The "load" signal is also the start outputting signal.
-- When it is high the value of data is taken in and  '1' is outputted
-- when it goes low the loaded data is sent out.
--
-- Once all the data has been sent "ready" goes high. 
--
-- The ispiration for this code, and part of the code was taken from
-- Darren O'Reilly and Jason Gunthorpe's code for their EE 552 project NARC (2000W)
--
-- The data rate is set by the clock period.
--
-- To change this code from odd to even parity see below for an
-- explaination

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity serialout is
	port(data : in std_logic_vector(6 downto 0);
		reset,
		clock,
		load : in std_logic;
		ready : buffer std_logic;
		serialoutput : out std_logic);
end serialout;

architecture behavioural of serialout is

	-- declare internal signals
	signal frame : std_logic_vector(10 downto 0);
	signal parity : std_logic;
	signal internaldata : std_logic_vector(6 downto 0);
	
begin

	-----------------------------------------------------------------
	-----------------------------------------------------------------
	-- To calculate the parity, the data is run through an xor
	-- gate.  Odd parity is this value NOTed, even is just this
	-- value.  Therefore, to convert this to even parity just
	-- remove the NOT.
	parity <= NOT(internaldata(0) xor internaldata(1) xor internaldata(2)
		  xor internaldata(3) xor internaldata(4) xor internaldata(5)
		  xor internaldata(6));

	-- The data frame consists of a 0 start bit, a 1
	-- stop bit, and a odd parity bit, 
	frame(0) <= '1'; 
	frame(1) <= '0';
	frame(8 downto 2) <= internaldata;
	frame(9) <= parity;
	frame(10) <= '1';
		
	sendout : process (clock) is

	-- process variable
	variable count:natural range 0 to 10;
	
	begin
		if rising_edge(clock) then
		if reset = '1' then
			internaldata <= (others => '0');
			ready <= '1';
			count:= 0;
			serialoutput <= frame(0);
		elsif load = '1' then
			ready <= '0';
			internaldata <= data;
			serialoutput <= frame(0);
			count:= 0;
		elsif ready = '1' then
			serialoutput <= frame(0);
		elsif count = 10 then
			ready <= '1';
			serialoutput <= frame(count);
			count:= 0;
		else
			count:= (count +1);
			serialoutput <= frame(count);
		end if;		
		end if;

	end process sendout;
end behavioural;