-----------------------------------------------------------------
-- serialin.vhd
-- Christopher Kowalski
--
-- RS-232 Serial Port In
--
-- The following VHDL code makes a RS-232 input port
-- It is  set up for:
-- Word Length:	7bits
-- Parity:	odd
-- Stop bits:	1
-- Data Rate:	9600 baud
--
-- When the entire data word has been read, and stored in a buffer
-- register, The "ready" signal goes high. It remains high until
-- "gotdata" is asserted meaning that the word has been read.  This
-- allows the input port to continuously take in data with out over-
-- writing the previous data as long as it is read with in 154 clock
-- cycles.
--
-- The clock rate should be set to 16 times the baud rate.
-- The start and stop bits are not passed out of the system.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity serialin is
	port(data : out std_logic_vector(7 downto 0);
		reset,
		clock,
		gotdata : in std_logic;
		ready : out std_logic;
		serialinput : in std_logic);
end serialin;

architecture behavioural of serialin is

	-- declare internal signals
	signal intdata : std_logic_vector(7 downto 0);	
	
begin
	
	starting : process (clock) is

	-- process variable
	variable count:natural range 0 to 154;
	
	begin
		if rising_edge(clock) then

		if reset = '1' then
			intdata <= (others => '0');
			ready <= '0';
			count:= 0;
			data <= (others => '0');
		elsif gotdata = '1' then
			ready <= '0';
			data <= (others => '0');
			if serialinput = '0' and count = 0 then
				count:= (count +1);
			elsif count /= 0 then
				count:=(count +1);
				
				case count is
				
				when 24 =>
					intdata(0) <= serialinput;
				when 40 =>
					intdata(1) <= serialinput;
				when 56 =>
					intdata(2) <= serialinput;
				when 72 =>
					intdata(3) <= serialinput;
				when 88 =>
					intdata(4) <= serialinput;
				when 104 =>
					intdata(5) <= serialinput;
				when 120 =>
					intdata(6) <= serialinput;
				when 136 =>
					intdata(7) <= serialinput;
				when 153 =>	
					data <= intdata;
				when 154 =>
					count:= 0;
					ready <= '1';
					intdata <= (others => '0');
				when others =>
					count:= count;
				end case;
			end if;

		elsif serialinput = '0' and count = 0 then
				count:= (count +1);
		elsif count /= 0 then
			count:=(count +1);
			case count is
			when 24 =>
				intdata(0) <= serialinput;
			when 40 =>
				intdata(1) <= serialinput;
			when 56 =>
				intdata(2) <= serialinput;
			when 72 =>
				intdata(3) <= serialinput;
			when 88 =>
				intdata(4) <= serialinput;
			when 104 =>
				intdata(5) <= serialinput;
			when 120 =>
				intdata(6) <= serialinput;
			when 136 =>
				intdata(7) <= serialinput;
			when 153 =>	
				data <= intdata;
			when 154 =>
				count:= 0;
				ready <= '1';
				intdata <= (others => '0');
			when others =>
				count:= count;
			end case;


		end if;
		end if;

	end process starting;
end behavioural;