---------------------------------------------------------
-- rs232test.vhd
-- Christopher Kowalski
--
-- RS-232 Serial Port, bi-directional
--
-- The following VHDL code makes a RS-232 port
-- It is  set up for:
-- Word Length:	7bits
-- Parity:	odd
-- Stop bits:	1
-- Data Rate:	9600 baud
--
-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package rs232_pack is 

	-- serial input section
	component serialin is
		port(data 		: out std_logic_vector(7 downto 0);
			reset,
			clock,
			gotdata 	: in std_logic;
			ready 		: out std_logic;
			serialinput : in std_logic);
	end component serialin;

	-- serial output section
	component serialout is
		port(data 		: in std_logic_vector(6 downto 0);
			reset,
			clock,
			load 		: in std_logic;
			ready 		: buffer std_logic;
			serialoutput: out std_logic);

	end component serialout;

	-- clock divider
	component clkdiv is
	Generic (Divisor1: positive :=1311;
             Divisor2: positive :=82 );
	PORT(fast_clock	: IN STD_LOGIC;
        reset      	: IN STD_LOGIC;
        slow_clock1 : BUFFER STD_LOGIC;
        slow_clock2	: BUFFER STD_LOGIC);
	end component clkdiv;

end package rs232_pack;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.rs232_pack.all; 

entity rs232test is
	port (	--serialinput,
			clock,
			reset,
			readinput,
			sendoutput		: in std_logic;
			serialout_in	: in std_logic_vector(6 downto 0);
			--serialoutput,
			gotinput		: out std_logic;
			sentoutput		: buffer std_logic;
			serialin_out	: out std_logic_vector(7 downto 0);
			fastclk,
			slowclk			: buffer std_logic;
			tied			: buffer std_logic

);
 	end rs232test;

architecture structural of rs232test is
-- declair internal signals
--signal fastclk	: std_logic;
--signal slowclk	: std_logic;


begin

	serin: component	serialin
				port map(data 	=> serialin_out,
						reset 	=> reset,
						clock 	=> fastclk,
						gotdata => readinput,
						ready 	=> gotinput,
						serialinput => tied);

	serout: component	serialout
				port map(data	=> serialout_in,
						reset	=> reset,
						clock	=> slowclk,
						load	=> sendoutput,
						ready	=> sentoutput,
						serialoutput => tied);
	
	clockscaler:	component	clkdiv
				port map(fast_clock	=> clock,
				        reset		=> reset,
				        slow_clock1 => slowclk,
				        slow_clock2 => fastclk);

end structural;