-------------------------------------------------
-- probeio_test.vhd
-- Christopher Kowalski
--
-- This is a test bench to test the probeIO.vhd code
--
-- This file is a modified from the adder_test.vhd
-- given in the EE552 lab.
--
--

library ieee;
use ieee.std_logic_1164.all;

package test_pkg is 

	------------------------------------------

	COMPONENT probeIO IS
	PORT (	
			clock,
			reset,
			serialinput,
			read,
			NewToSend		: in std_logic;
			DataToSend		: in std_logic_vector(4 downto 0);
			serialoutput,
			NewRecieved		: out std_logic;
			sent			: out std_logic;
			DataRecieved	: out std_logic_vector(4 downto 0));
 	END COMPONENT probeIO;
    
	------------------------------------------

end package test_pkg;

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.test_pkg.all;

-- textfixture
entity tester is
end tester;

architecture mixed of tester is

constant T_pw : time := 19 ns;
 

signal clock 		: std_logic;
signal reset 		: std_logic;
signal serialinput 	: std_logic;
signal read 		: std_logic;
signal NewToSend	: std_logic;
signal DataToSend	: std_logic_vector(4 downto 0) := (others => '0');
signal serialoutput	: std_logic;
signal NewRecieved	: std_logic;
signal sent			: std_logic;
signal DataRecieved	: std_logic_vector(4 downto 0) := (others => '0');

begin


	----------------------------------------

	probe_part : component probeIO 
		port map(
				clock			=> clock,
				reset			=> reset,
				serialinput		=> serialinput,
				read			=> read,
				NewToSend		=> NewToSend,
				DataToSend		=> DataToSend,
				serialoutput	=> serialoutput,
				NewRecieved		=> NewRecieved,
				sent			=> sent,
				DataRecieved	=> DataRecieved
			);
		----------------------------------------



	-- clock generator
	clock_gen : process
	begin
		clock <= '0' after T_pw, '1' after 2*T_pw;	
		wait for 2*T_pw;
	end process clock_gen;

	-- to reset the system at startup
	rst : process
	begin
		
	-- pulse reset to avoid "don't cares" on input 
		reset <= '0';
		wait for  10 ns;
		reset <= '1';
		wait for 60 us;
		reset <= '0';
		
		wait;
	end process rst;

	-- process to control handshaking signals and input
	ctrl_2 : process
	begin
		
		-- start of operation
		serialinput  <= '1';
		read <= '0';
		NewToSend <= '0';
		DataToSend <= (others => '0');
		wait for 100 us;

		-- Read a value to be sent out and start reading a input
		-- This code can handle any combination of inputs and outputs
		-- To change the data to be sent, just change the value in the
		-- quotes on the line: DataToSend <= "XXXXX"
		--
		-- To change the value read in change the value of the bit where
		-- serialinput is.  NOTE: The first bit must be '0' (Start Bit)
		-- and the last bit must be '1' (Stop Bit).

		DataToSend <= "10100";
		NewToSend <= '1';
		-- start bit, DO NOT CHANGE
		serialinput <= '0';
		wait for 104.167 us;

		-- MS data bit
		serialinput <= '0';
		wait for 104.167 us;


		NewToSend <= '0';
		-- data bit
		serialinput <= '1';
		wait for 104.167 us;

		-- data bit
		serialinput <= '1';
		wait for 104.167 us;

		-- data bit
		serialinput <= '0';
		wait for 104.167 us;

		-- data bit
		serialinput <= '1';
		wait for 104.167 us;

		-- data bit
		serialinput <= '1';
		wait for 104.167 us;

		-- data bit
		serialinput <= '0';
		wait for 104.167 us;

		-- parity bit
		serialinput <= '0';
		wait for 104.167 us;

		-- stot bit, DO NOT CHANGE
		serialinput <= '1';


		wait;
	end process ctrl_2;	

end mixed;