---------------------------------------------------------
-- probeIO.vhd
-- Christopher Kowalski
--
-- HI-4422 E-field probe I/O interfacer.
--
-- The following VHDL code is to interface with the e-field probe
-- It contains the following components:
-- 1. RS232
-- 2. ascii_to_vector
-- 3. vector_to_ascii
-- 4. paritychecher
--
-- Please see the code for these individual components for further
-- details in the operation of this interfacer.
--
-- Following the code is a brief description of it's operation.
--
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package probeIO_pack is 

	-- rs232 port
	component rs232 is
		port(serialinput,
			clock,
			reset,
			readinput,
			sendoutput		: in std_logic;
			serialout_in	: in std_logic_vector(6 downto 0);
			serialoutput,
			gotinput		: out std_logic;
			sentoutput		: buffer std_logic;
			serialin_out	: out std_logic_vector(7 downto 0));
	end component rs232;

	-- ASCII to vector decoder
	component ascii_to_vector  is
		port(ascii : in std_logic_vector(6 downto 0);
			reset,
			clock,
			transfer : in std_logic;
			done : out std_logic;
			vector : out std_logic_vector(4 downto 0));
	end component ascii_to_vector;

	-- vector to ASCII decoder
	component vector_to_ascii is
	port(ascii : out std_logic_vector(6 downto 0);
		reset,
		clock,
		load : in std_logic;
		done : out std_logic;
		vector : in std_logic_vector(4 downto 0));
	end component vector_to_ascii;

	-- a parity checker
	component paritychecker is
	port(ascii : in std_logic_vector(7 downto 0);
		reset,
		clock,
		load : in std_logic;
		transfer : out std_logic;
		asciiout : out std_logic_vector(6 downto 0));
	end component paritychecker;

end package probeIO_pack;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.probeIO_pack.all; 

entity probeIO is
	port (	clock,
			reset,
			serialinput,
			read,
			NewToSend		: in std_logic;
			DataToSend		: in std_logic_vector(4 downto 0);
			serialoutput,
			NewRecieved		: out std_logic;
			sent			: buffer std_logic;
			DataRecieved	: out std_logic_vector(4 downto 0));
 	end probeIO;

architecture structural of probeIO is
-- declair internal signals
signal intdone 		: std_logic;
signal intserialout	: std_logic_vector(6 downto 0);
signal intloaderror	: std_logic;
signal intdataerror	: std_logic_vector(7 downto 0);
signal interrorout	: std_logic_vector(6 downto 0);
signal inttransfer	: std_logic;
signal resetn		: std_logic;

begin
-- active low reset
resetn <= not(reset);


	rsport: component	rs232
				port map(serialinput	=> serialinput,
						clock			=> clock,
						reset			=> resetn,
						readinput		=> read,
						sendoutput		=> intdone,
						serialout_in	=> intserialout,
						serialoutput	=> serialoutput,
						gotinput		=> intloaderror,
						sentoutput		=> sent,
						serialin_out	=> intdataerror);




	astovec: component	ascii_to_vector
				port map(ascii 		=> interrorout,
						reset		=> resetn,
						clock		=> clock,
						transfer 	=> inttransfer,
						done		=> NewRecieved,
						vector 		=> DataRecieved);
	
	vectoas:	component	vector_to_ascii
				port map(ascii 		=> intserialout,
						reset		=> resetn,
						clock		=> clock,
						load	 	=> NewToSend,
						done		=> intdone,
						vector 		=> DataToSend);

	errcheck:	component	paritychecker
				port map(ascii		=> intdataerror,
						reset		=> resetn,
						clock		=> clock,
						load 		=> intloaderror,
						transfer	=> inttransfer,
						asciiout 	=> interrorout);


end structural;


--------------------------------------------------------------------------
-- The ProbeIO interface functions as follows:
--
-- The signals "Serialinput" and "serialoutput" are the input from the probe
-- and the output to the probe respectively.
--
-- Dealing with the output to the probe first:
--
-- The signal "NewToSend" is both a load and start signal for the probe
-- when the signal is raised high the value on the bus "DataToSend" is read into
-- a register.  When "NewtoSend" is returned registered data is latched and sent
-- through a Vector to ASCII converter and then send serially to to the porbe.
-- The parity is calculated as it is sent.  Once the data has been fully sent the
-- signal "sent" is asserted high, and will remain high until the signal "NewToSend"
-- is raised high again.  Sent goes high at Reset to indicate that new data is ready
-- to be sent.
--
-- Dealing with the input from the probe:
--
-- The signal "NewRecieved" goes high once a signal from the probe has been read
-- and converted from ASCII At this time a bus "DataRecieved" contains the encoded
-- ASCII value the probe sent.  When the signal "read" is asserted (hopefully after
-- the value has been read) the signal "NewRecieved" goes low again until a new 
-- value is read in from the probe.  NOTE:  If the value is not read before a new
-- character is fully sent from the probe, the old value will be overwritten with
-- the new value.
--
-- Please see the code for the ASCII converters for a converstion table.