-----------------------------------------------------------------
-- paritychecker.vhd
-- Christopher Kowalski
--
-- Parity Checker
-- This checks that the correct parity is recieved
-- Odd parity is checked for, see below to change to even parity
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity paritychecker is
	port(ascii : in std_logic_vector(7 downto 0);
		reset,
		clock,
		load : in std_logic;
		transfer : out std_logic;
		asciiout : out std_logic_vector(6 downto 0));
end paritychecker;

architecture behavioural of paritychecker is

	-- declare internal signals
	signal parity : std_logic;
	signal checker : std_logic;
	
begin

		
	check : process (clock) is

	-- process variable
	variable count:natural range 0 to 1;
	
	begin
		if rising_edge(clock) then
		if reset = '1' then
			asciiout <= (others => '0');
			transfer <= '0';
		elsif load = '1' then
			if count = 1 then
				if checker /= parity then
					asciiout <= "1111111";
 				else
					asciiout <= ascii(6 downto 0);
				end if;
			transfer <= '1';

			else
			checker <= ascii(7);
			-- To change to even parity remove the NOT below
			parity <= NOT(ascii(0) xor ascii(1)
					  xor ascii(2) xor ascii(3)
					  xor ascii(4) xor ascii(5)
		  			  xor ascii(6));
			count:= (count + 1);
			end if;
				
		elsif load = '0' then
			transfer <= '0';
			count := 0;
			

		end if;		
		end if;

	end process check;
end behavioural;