-------------------------------------------------------------
-- keydisplay.vhd
-- Christopher Kowalski
--
-- This controller reads the scan code off the keyboard and
-- outputs a coded bit vector.  This vector is then converted
-- into a display of the scan code on the two 7-segment led's on
-- the UP1 board
-- The buffer intdone is the least significant decimal point.
-- Having this signal allows the exploration of the typematic
-- and other functions of when a scan code is sent.
-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package keydisplay_pack is 

	-- keyboard input
	component keyboardcontrol is
		port(keyclock,
			clock,
			reset,
			keyboard	: in std_logic;
			done	 	: out std_logic;
			vector		: out std_logic_vector(3 downto 0));
	end component keyboardcontrol;

	-- scan code to vector decoder/coder
	component vector_to_7seg is
		port(vector		: in std_logic_vector(3 downto 0);
			reset,
			clock,
			done		: in std_logic;
			seg1 		: out std_logic_vector(6 downto 0);
			seg2 		: out std_logic_vector(6 downto 0));
	end component vector_to_7seg;

end package keydisplay_pack;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.keydisplay_pack.all; 

entity keydisplay is
	port (	keyclock,
			clock,
			reset,
			keyboard		: in std_logic;
			seg1			: out std_logic_vector(6 downto 0);
			seg2			: out std_logic_vector(6 downto 0);
			intdone			: buffer std_logic);
 	end keydisplay;

architecture structural of keydisplay is
-- declair internal signals
--signal intdone		: std_logic;
signal intvector	: std_logic_vector(3 downto 0);
signal notreset		: std_logic;

begin
notreset <= not(reset);

	keyread: component	keyboardcontrol
				port map(keyboard 	=> keyboard,
						reset 		=> notreset,
						keyclock 	=> keyclock,
						clock		=> clock,
						done		=> intdone,
						vector	 	=> intvector);

	codecon: component	vector_to_7seg
				port map(vector		=> intvector,
						reset		=> notreset,
						clock		=> clock,
						done		=> intdone,
						seg1		=> seg1,
						seg2		=> seg2);
	
end structural;