-------------------------------------------------------------
-- keyboardcontrol.vhd
-- Christopher Kowalski
--
-- PS2 Keyboard Controller (Actualy any AT Keyboard)
--
-- This controller reads the scan code off the keyboard and
-- outputs a coded bit vector.  See the code for the scan code
-- to vector decoder for a table of the scan codes read and the
-- matching vector.
--
-- The following control signals are used in the code:
-- Transfer: Once the keyboard was read in the entire scan code
-- 			this signal is asserted and remains high until a new
-- 			scan code is received.
-- Done:	This signal is raised high after the code conversion is
--			complete, and remains high until the "transfer" is lowered.
-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


package keyboard_pack is 

	-- keyboard input
	component key is
		port(keyboard,
			reset,
			keyclock	: in std_logic;
			scancode 	: out std_logic_vector(7 downto 0);
			gotcode		: out std_logic);
	end component key;

	-- scan code to vector decoder/coder
	component scancode_to_vector is
		port(scancode	: in std_logic_vector(7 downto 0);
			reset,
			clock,
			transfer	: in std_logic;
			done 		: out std_logic;
			vector 		: out std_logic_vector(3 downto 0));
	end component scancode_to_vector;

end package keyboard_pack;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.keyboard_pack.all; 

entity keyboardcontrol is
	port (	keyclock,
			clock,
			reset,
			keyboard		: in std_logic;
			done			: out std_logic;
			vector			: out std_logic_vector(3 downto 0));
 	end keyboardcontrol;

architecture structural of keyboardcontrol is
-- declair internal signals
signal intscancode	: std_logic_vector(7 downto 0);
signal inttransfer	: std_logic;

begin

	keyin: component	key
				port map(keyboard 	=> keyboard,
						reset 		=> reset,
						keyclock 	=> keyclock,
						scancode	=> intscancode,
						gotcode 	=> inttransfer);

	codeconvert: component	scancode_to_vector
				port map(scancode	=> intscancode,
						reset		=> reset,
						clock		=> clock,
						transfer	=> inttransfer,
						done		=> done,
						vector		=> vector);
	
end structural;