--clockdiv.vhd
-- modified by Christopher Kowalski
----------------------------------------------------
--divides down the system clock for slower clockrates
----------------------------------------------------
-- borrowed from traffic light example in EE552 class 
-- notes and modified to set the default to 9600 Hz and
-- 153600 Hz

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

ENTITY clkdiv IS
   -- default to 9600 Hz and 153.6 KHz
   -- 25.175 MHz/ 9600 / 2
   -- 25.175 MHz/ 153600 / 2
   Generic (Divisor1: positive :=1311; -- clock for sending
            Divisor2: positive :=82 );  -- clock for receiving
   PORT(fast_clock : IN STD_LOGIC;
        reset      : IN STD_LOGIC;
        slow_clock1 : BUFFER STD_LOGIC;
        slow_clock2:  BUFFER STD_LOGIC);
END clkdiv;

ARCHITECTURE behaviour OF clkdiv IS

BEGIN

   clock_divider: process (fast_clock) is
   variable c1:natural range 0 to Divisor1;
   variable c2:natural range 0 to Divisor2;
     
   BEGIN
      if fast_clock'EVENT and fast_clock = '1' then 
      if reset = '1' then
	  	 c1:= 0;
         c2:= 0;
         slow_clock1 <= not slow_clock1;  -- this creates a clock edge
		 slow_clock2 <= not slow_clock2;  -- for the sychronous reset in
      else   							  -- other parts of the project.
		 c1 := (c1 + 1);
         c2 := (c2 + 1);
         IF c1=Divisor1 THEN
            slow_clock1 <= not slow_clock1;
            c1 := 0;
         elsif c2 = Divisor2 then
            slow_clock2 <= not slow_clock2;
            c2:= 0;
         END IF;

		 

      end if;   
      end if;

   END PROCESS clock_divider;

END behaviour;