---------------------------------------------------------
-- cdutop.vhd
-- Christopher Kowalski
--
-- Top level of the CDU design
--
-- The following VHDL code is to interface with the e-field probe
-- It contains the following components:
-- 1. CmdDU.vhd
-- 2. main_display.vhd
-- 3. keyboardcontrol.vhd
--
-- Please see the code for these individual components for further
-- details on their operation.
--
--
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.display_pkg2.all;



package top_pack is 

	-- Command decision unit
	component CmdDU is
		port(reset,
			clock 			: in std_logic;
			Zoro			: in std_logic;
			NextRange		: in std_logic;
			NewReceived		: in std_logic; 
			DataReceived	: in std_logic_vector(4 downto 0);
			Read			: out std_logic;
			Sent			: in std_logic;
			DataSend		: out std_logic_vector(4 downto 0);
			NewToSend		: out std_logic;
			Volt_Value1		: out std_logic_vector(3 downto 0);
			Volt_Value2		: out std_logic_vector(3 downto 0);
			Volt_Value3		: out std_logic_vector(3 downto 0);
			Volt_Value4		: out std_logic_vector(3 downto 0);
			Volt_units		: out std_logic_vector(1 downto 0);
			Volt_range		: out std_logic_vector(1 downto 0);
			Axis_enabled	: out std_logic_vector(2 downto 0);
			Over_range		: out std_logic;
			Bat_Value1		: out std_logic_vector(3 downto 0);
			Bat_Value2		: out std_logic_vector(3 downto 0);
			Bat_Value3		: out std_logic_vector(3 downto 0);
			Bat_Value4		: out std_logic_vector(3 downto 0);
			Bat_status		: out std_logic_vector(1 downto 0);
--			Temp_Value1		: out std_logic_vector(3 downto 0);
--			Temp_Value2		: out std_logic_vector(3 downto 0);
			Zeroed			: out std_logic
--			noise			: buffer std_logic
			);
	end component CmdDU;
	
	-- clock halver
	component clkdiv is
	port(fast_clock : in std_logic;
		reset : in std_logic;
        slow_clock1 : buffer std_logic);
    end component clkdiv;

end package top_pack;

---------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.top_pack.all;
use work.display_pkg2.all; 

entity cdutop is
	port (	clock,
			reset,
			Zoro,
			NextRange	: in std_logic;
			DataToSend	: out std_logic_vector(4 downto 0);
			NewToSend	: out std_logic;
			sent		: in std_logic;
			DataRecieved : in std_logic_vector(4 downto 0);
			read		: out std_logic;
			NewRecieved	: in std_logic;
			Noise		: buffer std_logic;
			vga_red,
			vga_blue,
			vga_green	: out boolean;
			HSync,
			VSync		: out std_logic);
 	end cdutop;

architecture structural of cdutop is

-- declair internal signals
signal 	resetn			: std_logic; 
signal 	intkey_done		: std_logic;
signal	intkey_command	: std_logic_vector(3 downto 0);
signal 	intvolt1		: std_logic_vector(3 downto 0);
signal 	intvolt2		: std_logic_vector(3 downto 0);
signal 	intvolt3		: std_logic_vector(3 downto 0);
signal 	intvolt4		: std_logic_vector(3 downto 0);
signal 	intvoltu		: std_logic_vector(1 downto 0);
signal 	intvoltr		: std_logic_vector(1 downto 0);
signal 	intaxis			: std_logic_vector(2 downto 0);
signal 	intoverrange	: std_logic;
signal 	intbat1			: std_logic_vector(3 downto 0);
signal 	intbat2			: std_logic_vector(3 downto 0);
signal 	intbat3			: std_logic_vector(3 downto 0);
signal 	intbat4			: std_logic_vector(3 downto 0);
signal 	intbatsat		: std_logic_vector(1 downto 0);
signal	inttemp1		: std_logic_vector(3 downto 0);
signal	inttemp2		: std_logic_vector(3 downto 0);
signal	intzero			: std_logic;
signal	intclk_2		: std_logic;

begin
-- reset is active low
resetn <= not(reset);

	command: component	CmdDU
		port map(reset			=> resetn,
				clock 			=> intclk_2,
				Zoro			=> Zoro,
				NextRange		=> NextRange,
				NewReceived		=> NewRecieved, 
				DataReceived	=> DataRecieved,
				Read			=> Read,
				Sent			=> sent,
				DataSend		=> DataToSend,
				NewToSend		=> NewToSend,
				Volt_Value1		=> intvolt1,
				Volt_Value2		=> intvolt2,
				Volt_Value3		=> intvolt3,
				Volt_Value4		=> intvolt4,
				Volt_units		=> intvoltu,
				Volt_range		=> intvoltr,
				Axis_enabled	=> intaxis,
				Over_range		=> intoverrange,
				Bat_Value1		=> intbat1,
				Bat_Value2		=> intbat2,
				Bat_Value3		=> intbat3,
				Bat_Value4		=> intbat4,
				Bat_status		=> intbatsat,
--				Temp_Value1		=> inttemp1,
--				Temp_Value2		=> inttemp2,
				Zeroed			=> intzero
--				noise			=> Noise
);

	clockdiv:	component clkdiv
		port map(fast_clock	=> clock,
				reset	=> resetn,
        		slow_clock1	=> intclk_2);

	display: component probedisplay
		port map(clock			=> clock,
				vga_red			=> vga_red,
				vga_green		=> vga_green,
				vga_blue		=> vga_blue,
				HSync			=> HSync,
				VSync			=> VSync,
		        volt_value1		=> intvolt1,
				volt_value2		=> intvolt2,
				volt_value3		=> intvolt3,
				volt_value4 	=> intvolt4,
		        volt_units		=> intvoltu,
				volt_range 		=> intvoltr,
        		axis_enabled 	=> intaxis,
	        	over_range		=> intoverrange,
				zeroed			=> intzero,
	    	    bat_value1		=> intbat1,
				bat_value2		=> intbat2,
				bat_value3		=> intbat3,
				bat_value4 		=> intbat4,
        		bat_status 		=> intbatsat,
--        		temp_value1		=> inttemp1,
--				temp_value2 	=> inttemp2,
				reset			=> reset,
				noise			=> Noise);	-- set to active low in code
	

end structural;