-- Interactive Audio Manipulation Processor
--
-- file: syncgen.vhd
-- status: compiled - no errors (but I get glitches on some monitors)
--
-- author: see reference [7]
--
-- Except for this header, this file is a verbatim copy of syncgen.vhd
-- from the Pong game by reference [7] in the report. See this URL:
-- http://www.jps.net/kyunghi/up1board.htm

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY SyncGen IS
	PORT
	(
		Clock			: IN	STD_LOGIC;
		HSync, VSync		: OUT	BOOLEAN;
		vclock			: OUT   STD_LOGIC;
		vga_h_sync, vga_v_sync	: OUT	BOOLEAN
	);
END SyncGen;

ARCHITECTURE ASyncGen OF SyncGen IS
	SIGNAL	CounterX, CounterY: INTEGER RANGE 0 TO 1023;
	SIGNAL	HS, VS, vga_HS, vga_VS: BOOLEAN;
BEGIN
	PROCESS (Clock)
	VARIABLE
		EnableCntY, ResetCntY: BOOLEAN;
	BEGIN
		EnableCntY := (CounterX=40);
		ResetCntY := (CounterY=524);

		IF Clock'EVENT AND Clock='1' THEN
			IF CounterX=799 THEN
				CounterX <= 0;
			ELSE
				CounterX <= CounterX + 1;
			END IF;

			IF EnableCntY THEN
				IF ResetCntY THEN
					CounterY <= 0;
				ELSE
					CounterY <= CounterY + 1;
				END IF;
			END IF;

			vga_HS <= (CounterX<96);
			vga_VS <= (CounterY< 2);
			HS <= (CounterX=128);
			VS <= (CounterY= 32) AND HS;
		END IF;
	END PROCESS;

	vga_h_sync <= vga_HS;
	vga_v_sync <= vga_VS;
	HSync <= HS;
	VSync <= VS;
	vclock<= '1' when VS;

END ASyncGen;