-- Interactive Audio Manipulation Processor
--
-- file: ram_interface2.vhd
-- status: not compiled
--
-- author: Stephen Tang
--
-- This entity interfaces with the RAM driver (ram_port), the ADC driver
-- (adc_port), and the audio manipulation path (audio_manipulator). The
-- RAM interface accepts samples from the ADC and saves the samples in
-- RAM, and outputs those samples to the audio manipulator upon request.
--
-- ram_interface2 is a stub that simply passes the most recent data from
-- the ADC on to the audio path, regardless of sample delay requested by
-- the audio path.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library work;
use work.Constants_Pkg.all;

entity ram_interface2 is
  port (
    clock: in std_logic; -- should be 25.175MHz
    reset: in std_logic; -- active low, from reset pushbutton
    
    -- RAM interface
    ram_ack_in: in std_logic;   -- RAM driver has serviced the request
    ram_request: out std_logic; -- request services of RAM driver
    ram_rw: out std_logic;      -- indicate request type: R (1) or W (0)
    ram_address: buffer std_logic_vector(RAM_ADDRESS_WIDTH-1 downto 0);
    ram_data: inout std_logic_vector(RAM_DATA_WIDTH-1 downto 0);
    
    -- ADC interface
    adc_ready: in std_logic;  -- ADC has a sample ready
    adc_ack: out std_logic;   -- tell ADC that the sample was received
    adc_sample_in: in std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0);
      -- incoming sample from ADC; note that only the most-significant
      -- 8 bits out of the 24 total are input to the RAM interface!
    
    -- audio path interface
    a_delay: in std_logic_vector(DELAY_WIDTH-1 downto 0);
      -- delay of the sample to retrieve
    a_request: in std_logic; -- audio path wants a sample
    a_ack: out std_logic;    -- sample has been sent
    a_sample: out std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0)
      -- the sample requested by the audio path
  );
end ram_interface2;

architecture RAMinterface of ram_interface2 is

begin
  ram_rw <= '1';
  ram_data <= (others => 'Z');
  ram_address <=(others => '0');

  dummy: process(clock)
  begin
    if a_request <= '1' then
      a_ack <= '1';
    else
      a_ack <= '0';
    end if;
    if adc_ready = '1' then
      adc_ack <= '1';
    else
      adc_ack <= '0';
    end if;
  end process dummy;

    ram_request <= '0';
    a_sample <= adc_sample_in(EFFECTIVE_SAMPLE_WIDTH-1 downto 0);
end;