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--	multiplier.vhd
-------------------------------------

-- Use IEEE Libraries.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Declare entity. Clock is the clock pulse, Reset starts the
-- multiplier and sets the 'done' bit low.
-- input1 and input2 are the two n-bit inputs.
-- When the multiplier is finished, the done bit goes high.

entity multiplier is
	generic (bitwidth : positive := 15);
	port (clock, reset : in std_logic;
		 done_out : out std_logic;
		 input1, input2 : in std_logic_vector(bitwidth-1 downto 0);
		 input1sign, input2sign : in std_logic;
		 output : out std_logic_vector(2*bitwidth-1 downto 0);
		 outputsign : out std_logic
		);
end multiplier;

-- We will use a state machine to control our multiplier, which
-- takes advantage of components such as shift registers and
-- adder/subtractors.

architecture behavioral of multiplier is
-- component declarations.

-- shift register component.

component singleshiftregister
	port	(load, do_shift, shiftin, reset, clock : in std_logic;
			 shiftout : out std_logic;
			 Reg_in : in std_logic;
			 Reg_out : out std_logic
			);
end component;

component shiftregister
	generic ( bitwidth : positive);
	port	(load, do_shift, shiftin, reset, clock : in std_logic;
			 shiftout : out std_logic;
			 Reg_in : in std_logic_vector(bitwidth-1 downto 0);
			 Reg_out : out std_logic_vector(bitwidth-1 downto 0)
			);
end component;

-- synchronous adder component

component mult_adder
	generic (bitwidth : positive := 15);
	port (addend1, addend2 : in std_logic_vector (bitwidth-1 downto 0);
		 sum : out std_logic_vector (bitwidth-1 downto 0);
		 cin : in std_logic;
		 cout : out std_logic
		);	
end component;

-- counter component

component counter
	generic (bitwidth : positive := 15);
	port (count, clock, reset : in std_logic; 
	done : out std_logic);
end component;	

-- controller component

component mult_control
	port (resetin, clock, done, control_bit: in std_logic;
	loadG, loadP, loadQ, loadR, resetG, resetP, resetQ, resetR, reset_counter, count, shift: out std_logic
	);
end component;

signal GReg_to_PReg : std_logic;
signal PReg_to_QReg : std_logic;
signal Control_bit : std_logic;
signal Adder_Cout : std_logic;
signal Adder_Sum, P_Out, R_Out : std_logic_vector(bitwidth-1 downto 0);
signal loadG, loadP, loadQ, loadR : std_logic;
signal reset_adder, resetG, resetP, resetQ, resetR, reset_counter : std_logic;
signal do_add, shiftsignal : std_logic;
signal count, done : std_logic;
signal ground : std_logic;
signal highz : std_logic;
begin

highz <= 'Z';
ground <= '0';
Output(2*bitwidth-1 downto bitwidth) <= P_Out;
done_out <= done;
outputsign <= input1sign xor input2sign;

GReg: singleshiftregister
	port map (
	load => LoadG,
	do_shift => shiftsignal,
	shiftin => ground,
	reset => ResetG,
	clock => clock,
	shiftout => GReg_to_PReg,
	Reg_in => adder_cout
	);
	

QReg: shiftregister
	generic map(bitwidth)
	port map (
	load => LoadQ,
	do_shift => shiftsignal,
	shiftin => PReg_to_QReg,
	reset => ResetQ,
	clock => clock,
	shiftout => control_bit,
	Reg_in => Input2,
	Reg_out => Output(bitwidth-1 downto 0)
	);

PReg: shiftregister
	generic map(bitwidth)
	port map (
	load => LoadP,
	do_shift => shiftsignal,
	shiftin => GReg_to_PReg,
	reset => ResetP,
	clock => clock,
    shiftout => PReg_to_QReg,
	Reg_in => Adder_Sum,
	Reg_out => P_Out
	);

RReg: shiftregister
	generic map(bitwidth)
	port map (
	load => LoadR,
	do_shift => ground,
	shiftin => ground,
	reset => ResetR,
	clock => clock,
--  shiftout => highz,
	Reg_in => Input1,
	Reg_out => R_Out
	);


Adder: mult_adder
	generic map(bitwidth)
	port map (
	addend1 => P_Out,
	addend2 => R_Out,
	sum => Adder_Sum,
	cin => ground,
	cout => adder_cout
	);


Shift_Counter: counter
	port map (
	count => count,
	clock => clock,
	reset => reset_counter,
	done => done
	);	

Controller: mult_control
	port map (
	resetin => reset,
	clock => clock,
	done => done,
	control_bit => control_bit,
	loadG => loadG,
	loadP => loadP,
	loadQ => loadQ,
	loadR => loadR,
	resetG => resetG,
	resetP => resetP,
	resetQ => resetQ,
	resetR => resetR,
	reset_counter => reset_counter,
	count => count,
	shift => shiftsignal
	);

end behavioral;