------------------------------------- -- mult_control.vhd -- Multiplier Controller -- -- February 26, 2000 -- Ross, Daniel 355951 -- -- This entity controls the -- signed integer multiplier -- entity. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mult_control is port (resetin, clock, done, control_bit: in std_logic; loadG,loadP,loadQ,loadR: out std_logic; resetG,resetP,resetQ,resetR,reset_counter: out std_logic; count,shift: out std_logic ); end mult_control; architecture behavioral of mult_control is -- Finite state machine states type states is (idle, initialize, add, shiftcount); signal current_state, next_state : states; begin combinational_logic : process (current_state, next_state, resetin, clock, done, control_bit) begin case current_state is when idle => -- nothing happens here. loadG <= '0'; loadP <= '0'; loadQ <= '0'; loadR <= '0'; resetG <= '0'; resetP <= '0'; resetQ <= '0'; resetR <= '0'; reset_counter <= '0'; count <= '0'; shift <= '0'; -- next state if resetin = '1' then next_state <= initialize; else next_state <= idle; end if; when initialize => -- we will reset Registers G and P, and load Q and R. -- we will also reset our counter and adder. loadG <= '0'; loadP <= '0'; loadQ <= '1'; loadR <= '1'; resetG <= '1'; resetP <= '1'; resetQ <= '0'; resetR <= '0'; reset_counter <= '1'; count <= '0'; shift <= '0'; if resetin = '1' then next_state <= initialize; elsif control_bit = '1' then next_state <= add; else next_state <= shiftcount; end if; when add => -- The sum of R and P will go into P. loadG <= '0'; loadP <= '1'; loadQ <= '0'; loadR <= '0'; resetG <= '0'; resetP <= '0'; resetQ <= '0'; resetR <= '0'; reset_counter <= '0'; count <= '0'; shift <= '0'; if resetin = '1' then next_state <= initialize; else next_state <= shiftcount; end if; when shiftcount => -- we will count up one and shift all our stuff. loadG <= '0'; loadP <= '0'; loadQ <= '0'; loadR <= '0'; resetG <= '0'; resetP <= '0'; resetQ <= '0'; resetR <= '0'; reset_counter <= '0'; count <= '1'; shift <= '1'; if resetin = '1' then next_state <= initialize; elsif done = '1' then next_state <= idle; elsif control_bit = '1' then next_state <= add; else next_state <= shiftcount; end if; end case; end process combinational_logic; state_register : process(resetin, clock, current_state) begin if rising_edge(clock) then -- advance to next state current_state <= next_state; end if; end process state_register; end behavioral;