-------------------------------------
--	mult_adder.vhd
--	Synchronous Adder.
--
--	February 22, 1999
--	Carter, Todd
--
--	This adds two n-bit
--	numbers together, with a
--	carry in, a carry out. 

library ieee;
use ieee.std_logic_1164.all;

entity mult_adder is
	generic (bitwidth : positive := 15);
	port (addend1, addend2 : in std_logic_vector (bitwidth-1 downto 0);
		 sum : out std_logic_vector (bitwidth-1 downto 0);
		 cin : in std_logic;
		 cout : out std_logic
		);
end mult_adder;

library ieee;
use ieee.std_logic_1164.all;

Package and_2_package IS
    component and_2
        port (a    : in std_logic;
              b    : in std_logic;
              c    : out std_logic);
    end component;
end and_2_package;

LIBRARY work;
use work.and_2_package.ALL;

-- structural implementation of the N-bit adder
architecture structural of mult_adder is

    signal carry : std_logic_vector(bitwidth downto 0);

begin
    carry(0) <= cin;
    cout <= carry(bitwidth);

    -- instantiate a single-bit adder N times
    gen: for I in 0 to bitwidth-1 generate
	add: adder port map(
		a => addend1(I),
		b => addend2(I),
		cin => carry(I),
		sum => sum(I),
		cout => carry(I+1));
   end generate;
end structural;