-- Interactive Audio Manipulation Processor -- -- file: main.vhd -- status: compiled -- no errors -- -- author: Stephen Tang -- -- This file contains the top-level entity of the entire iAMP design. -- main routes all of the signals between the external hardware and -- the top-level entities of the system. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.Constants_Pkg.all; entity main is port ( -- universal signals clk : in std_logic; --system clock, 25.175MHz; pin 91 rst : in std_logic; -- reset signal from pushbutton FLEX_PB1, pin 28 -- video signals vga_red, vga_green, vga_blue: out boolean; -- pins 236, 237, 238 (VGA 15-pin D-sub) vga_h_sync,vga_v_sync : buffer boolean; -- pins 240 and 239 (VGA 15-pin D-sub) -- joystick signals Jup, Jdown, Jleft, Jright, Jfire: in std_logic; -- pins 100, 98, 95, 88, 86 (holes 55,53,51,49,47 on FLEX_EXPAN_A) -- SRAM signals -- ad: inout std_logic_vector(RAM_ADDRESS_WIDTH-1 downto 0); -- da: inout std_logic_vector(RAM_DATA_WIDTH-1 downto 0); -- r_w: inout std_logic; -- oe, cs: out std_logic; -- ADC signals with variable values mclka: out std_logic; lrcka, sclka: in std_logic; sdata_adc, frame: in std_logic; rst_adc: out std_logic; -- DAC signals with variable values mclk0, mclk1, lrck0, lrck1: out std_logic; sclk0, sclk1: buffer std_logic; sdata_dac0, sdata_dac1: out std_logic; -- DAC signals that remain constant muteR0, muteR1, muteL0, muteL1, amute0, amute1: out std_logic; vcc_dac, gnd_dac: out std_logic ); end main; architecture Structural of main is component ui is port ( clk : in std_logic; --system clock, 25.175MHz; pin 91 rst : in std_logic; -- reset signal from pushbutton FLEX_PB1, pin 28 SlowClk: in std_logic; vga_red, vga_green, vga_blue: out boolean; -- pins 236, 237, 238 vga_h_sync,vga_v_sync : buffer boolean;-- pins 240 and 239 Jup, Jdown, Jleft, Jright, Jfire: in std_logic; sound_x, sound_y: out std_logic_vector(SOURCE_WIDTH-1 downto 0) ); end component; component GenerateSlowClocks is port ( clock: in std_logic; clock2, clock512: out std_logic ); end component; -- the following commented-out components have not been integrated yet -- component ram_port is -- port ( -- clock : in std_logic; -- ad_out : out std_logic_vector(18 downto 0); -- da_out : inout std_logic_vector(7 downto 0); -- r_w_out : out std_logic; -- oe_out : out std_logic; -- cs_out : out std_logic; -- da_in : inout std_logic_vector(7 downto 0); -- ad_in : in std_logic_vector(18 downto 0); -- r_w_in : in std_logic; -- ack_in : in std_logic; -- ack_out : out std_logic -- ); -- end component; component dac_port is port ( -- systemclock, sampleclock256 : in std_logic; clock : in std_logic; reset : in std_logic; s_data : out std_logic; s_clock : buffer std_logic; m_clock: out std_logic; lr_clock: out std_logic; left_right: in std_logic; data : in std_logic_vector(SAMPLE_WIDTH-1 downto 0); ack_in : in std_logic; ack_out : out std_logic ); end component; component adc is port(clock : in std_logic; -- sampleclock256, systemclock, reset : in std_logic; reset : in std_logic; reset_adc : out std_logic; s_data : in std_logic; s_clock : in std_logic; m_clock : out std_logic; lr_clock : in std_logic; sample : out std_logic_vector(23 downto 0); --SAMPLE_WIDTH-1 ack_in : in std_logic; ack_out : out std_logic; data_count_temp : buffer std_logic_vector(4 downto 0) ); end component; component dac_interface is port ( clock, reset: in std_logic; speakerFL, speakerFR, speakerBL, speakerBR: std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0); left_right: std_logic; sample0, sample1: std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0); ack_in0, ack_out0, ack_in1, ack_out1: std_logic ); end component; component audio_manipulator is generic (bitwidth : positive := 8; -- 24 bit samples. loc_bitwidth : positive := 4; -- 4 bit location unsigned integers. gain_bitwidth : positive := 4; -- 4 bit gain unsigned integers. delay_bitwidth : positive := 5; -- delay is up to 31*128 =3968 -- samples (or .1 of a second.) samples : positive := 2; -- 2^3 = 8 samples per sample_clock period. regwidth : positive := 4 ); port ( system_clock : in std_logic; sample_clock : in std_logic; reset : in std_logic; Xloc : in std_logic_vector(loc_bitwidth-1 downto 0); Yloc : in std_logic_vector(loc_bitwidth-1 downto 0); Delay : out std_logic_vector(delay_bitwidth-1 downto 0); Sample_Req : out std_logic; Data_Ready : in std_logic; Sample_In : in std_logic_vector(bitwidth-1 downto 0); Speaker00, Speaker01, Speaker10, Speaker11 : out std_logic_vector(bitwidth-1 downto 0) ); end component; component ram_interface2 is port ( clock: in std_logic; -- should be 25.175MHz reset: in std_logic; -- active low, from reset pushbutton -- RAM interface ram_ack_in: in std_logic; -- RAM driver has serviced the request ram_request: out std_logic; -- request services of RAM driver ram_rw: out std_logic; -- indicate request type: R (1) or W (0) ram_address: buffer std_logic_vector(RAM_ADDRESS_WIDTH-1 downto 0); ram_data: inout std_logic_vector(RAM_DATA_WIDTH-1 downto 0); -- ADC interface adc_ready: in std_logic; -- ADC has a sample ready adc_ack, rst_adc: out std_logic; -- tell ADC that the sample was received adc_sample_in: in std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0); -- incoming sample from ADC; note that only the most-significant -- 8 bits out of the 24 total are input to the RAM interface! -- audio path interface a_delay: in std_logic_vector(DELAY_WIDTH-1 downto 0); -- delay of the sample to retrieve a_request: in std_logic; -- audio path wants a sample a_ack: out std_logic; -- sample has been sent a_sample: out std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0) -- the sample requested by the audio path ); end component; -- glue signals to tie components together signal clock2, clock512: std_logic; signal ActiveHighReset: std_logic; -- ties ui to audio_path signal SoundLocationX: std_logic_vector(SOURCE_WIDTH-1 downto 0); signal SoundLocationY: std_logic_vector(SOURCE_WIDTH-1 downto 0); -- RAM signals that will no longer be used signal RamDone, RamRequest, RamRW: std_logic; signal RamAddress: std_logic_vector(RAM_ADDRESS_WIDTH-1 downto 0); signal RamData: std_logic_vector(RAM_DATA_WIDTH-1 downto 0); -- ties ADC to RAM to audio_manipulator signal SampleFromRamInterface: std_logic_vector(RAM_DATA_WIDTH-1 downto 0); signal AdcSampleReady, AdcSampleAccepted: std_logic; signal AdcSample: std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0); signal AudioSampleRequest, SampleSentToAudio: std_logic; signal Delay: std_logic_vector(5-1 downto 0); -- ties audio manipulator to DAC signal Speaker00, Speaker01, Speaker10, Speaker11, DacSample0, DacSample1: std_logic_vector(EFFECTIVE_SAMPLE_WIDTH-1 downto 0); signal LeftRight: std_logic; signal DacAckOut0, DacAckIn0, DacAckOut1, DacAckIn1: std_logic; -- temp signals signal fake_data: std_logic_vector(SAMPLE_WIDTH-1 downto 0); signal one, zero: std_logic; begin -- Structural ActiveHighReset <= not rst; UserInterface: ui port map ( clk => clk, rst => rst, SlowClk => clock2, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, vga_h_sync => vga_h_sync, vga_v_sync => vga_v_sync, Jup => Jup, Jdown => Jdown, Jleft => Jleft, Jright => Jright, Jfire => Jfire, sound_x => SoundLocationX, sound_y => SoundLocationY ); MakeSlowClocks: GenerateSlowClocks port map ( clock => clk, clock2 => clock2, clock512 => clock512 ); DtoA0: dac_port port map ( -- sampleclock256 => sclk, clock => clk, reset => ActiveHighReset, s_data => sdata_dac0, s_clock => sclk0, m_clock => mclk0, lr_clock => lrck0, left_right => LeftRight, data => DacSample0, ack_in => DacAckIn0, ack_out => DacAckOut0 ); -- temp! fake_data <= "011111001010101010101111"; one <= '1'; zero <= '0'; muteL0 <= '1'; muteL1 <= '1'; muteR0 <= '1'; muteR1 <= '1'; amute0 <= '0'; amute1 <= '0'; vcc_dac <= '1'; gnd_dac <= '0'; FakeLR: process(sclk0) variable LRcount: std_logic_vector(5 downto 0); begin if rising_edge(sclk0) then if rst = '0' then -- active low reset! LeftRight <= '0'; LRcount := "000000"; else if LRcount = "10111" then -- equals 23 LeftRight <= not LeftRight; LRcount := "000000"; else LRcount := LRcount + '1'; end if; end if; end if; end process FakeLR; DtoA1: dac_port port map ( clock => clk, reset => ActiveHighReset, s_data => sdata_dac1, s_clock => sclk1, m_clock => mclk1, lr_clock => lrck1, left_right => LeftRight, data => DacSample1, ack_in => DacAckIn1, ack_out => DacAckOut1 ); -- sampleclock256 => sclk, -- frame => frame, -- st_clock => sclk, AtoD: adc port map ( -- sampleclock256 => sclk, clock => clk, reset => ActiveHighReset, reset_adc => rst_adc, s_data => sdata_adc, s_clock => sclka, m_clock => mclka, lr_clock => lrcka, sample => AdcSample, ack_in => AdcSampleAccepted, ack_out => AdcSampleReady ); theAudio: audio_manipulator port map ( system_clock => clk, sample_clock => Clock512, reset => ActiveHighReset, Xloc => SoundLocationX, Yloc => SoundLocationY, Delay => Delay, Sample_Req => AudioSampleRequest, Data_Ready => SampleSentToAudio, Sample_In => SampleFromRamInterface, Speaker00 => Speaker00, Speaker01 => Speaker01, Speaker10 => Speaker10, Speaker11 => Speaker11 ); AudioToDAC: dac_interface port map ( clock => clk, reset => rst, speakerFL => Speaker00, speakerFR => Speaker01, speakerBL => Speaker10, speakerBR => Speaker11, left_right=> LeftRight, sample0 => DacSample0, sample1 => DacSample1, ack_in0 => DacAckOut0, ack_out0 => DacAckIn0, ack_in1 => DacAckOut1, ack_out1 => DacAckIn1 ); RAMinterface: ram_interface2 port map ( clock => clock2, reset => rst, ram_ack_in => RamDone, ram_request => RamRequest, ram_rw => RamRW, ram_address => RamAddress, ram_data => RamData, adc_ready => AdcSampleReady, adc_ack => AdcSampleAccepted, adc_sample_in => AdcSample, a_delay => Delay, a_request => AudioSampleRequest, a_ack => SampleSentToAudio, a_sample => SampleFromRamInterface ); -- tie off RAM signals, which are no longer needed RamDone <= '0'; --RamData <= (others => '0'); -- no longer used -- TheRAM: ram_port port map ( -- clock => clock2, -- ad_out => ad, -- da_out => da, -- r_w_out => r_w, -- oe_out => oe, -- cs_out => cs, -- da_in => da, -- ad_in => ad, -- r_w_in => r_w, -- ack_in => ?, -- ack_out => ? -- ); end Structural;