-------------------------------------
--	mult_adder.vhd
--	Synchronous Adder.
--
--	February 26, 2000
--	Ross, Daniel 355951
--
--	This adds two n-bit
--	numbers together, with a
--	carry in, a carry out. The
--	output only updates if
--	do_add is high on a clock
--	pulse.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ez_mult is
	generic (bitwidth : positive := 15);
	port (addend1, addend2 : in std_logic_vector (bitwidth-1 downto 0);
		 sum : out std_logic_vector (2*bitwidth-1 downto 0)
		);
end ez_mult;

architecture behavioral of ez_mult is


signal sum1: std_logic_vector(2*bitwidth-1 downto 0);

begin

update_output: process

begin

sum1 <= addend1 * addend2;

end process update_output;

output_process: process
begin

sum(2*bitwidth-1 downto 0) <= sum1(2*bitwidth-1 downto 0);


end process output_process;

end behavioral;