-------------------------------------
--	counter.vhd
--	Counter/Comparator.
--
--	February 26, 2000
--	Ross, Daniel 355951
--
--	This compares an adder
--	sum and the bitwidth,
--	and takes 'done' high
--	when the adder sum
--	is >= bitwidth.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
	generic (bitwidth : positive := 15);
	port (count, clock, reset : in std_logic; done : out std_logic);
end counter;	

architecture behavioral of counter is

signal sum: std_logic_vector(bitwidth/2-2 downto 0);

begin

increment: process
begin
wait until rising_edge(clock);
if (reset = '1') then
	sum <= (others=> '0');
elsif (count = '1' ) then
	sum <= sum + 1;
end if;
end process increment;

isitdone: process
begin
wait until falling_edge(clock);
if (sum >= bitwidth) then
	done <= '1';
else
	done <= '0';
end if;
end process isitdone;

end behavioral;