-------------------------------------
--	audio_manipulator.vhd
--	Audio Manipulator
--
--	March 14, 2000
--	Ross, Daniel 355951
--	Status: 
--
--	This entity contains the audio
--	controller (audio_controller.vhd)
--	and the audio path that it controls.
--	
--	16-bit samples are captured and
--	stored in registers Reg0_0 to Reg0_3.
--	On the sample_clock rising edge, these
--	are then placed into Reg1_0 through
--	Reg1_3. These are then multiplied by a
--	gain factor one at a time and placed
--	in Reg2_0 through Reg2_3. 
--	These registers are the output of the
--	Audio Manipulator (which feeds the DACs.)


-- Use IEEE Libraries.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Declare entity. 

entity audio_manipulator is
	generic (bitwidth : positive := 8; -- 24 bit samples.
			loc_bitwidth : positive := 4; -- 4 bit location unsigned integers.
			gain_bitwidth : positive := 4; -- 4 bit gain unsigned integers.
			delay_bitwidth : positive := 5; -- delay is up to 31*128 =3968 
											-- samples (or .1 of a second.)
			samples : positive := 2; -- 2^3 = 8 samples per sample_clock period.
			regwidth : positive := 4
	);
	port (
		system_clock : in std_logic;
		sample_clock : in std_logic;
		reset : in std_logic;
		
		Xloc : in std_logic_vector(loc_bitwidth-1 downto 0);
		Yloc : in std_logic_vector(loc_bitwidth-1 downto 0);

		Delay : out std_logic_vector(delay_bitwidth-1 downto 0);
		Sample_Req : out std_logic;
		Data_Ready : in std_logic;

		Sample_In : in std_logic_vector(bitwidth-1 downto 0);
		Speaker00, Speaker01, Speaker10, Speaker11 : out std_logic_vector(bitwidth-1 downto 0)		
		);
end audio_manipulator;

architecture audio_manipulator of audio_manipulator is

-- component declarations follow.

component mymux
	generic (bitwidth : positive);
	port (I0, I1, I2, I3: in std_logic_vector(bitwidth-1 downto 0);
		  Sel : in std_logic_vector(1 downto 0);
		  MUXOut : out std_logic_vector(bitwidth-1 downto 0)
		);
end component;

component myselector2
	port (I0, I1, I2, I3: out std_logic;
		  Sel : in std_logic_vector(1 downto 0);
		  SelectorIn : in std_logic
		);
end component;

component myregister
	generic (bitwidth : positive);
	port(reset, clock : in std_logic;
		 Reg_in : in std_logic_vector(bitwidth-1 downto 0);
		 Reg_out : out std_logic_vector(bitwidth-1 downto 0)
		);
end component;

component gain_mult
	generic (bitwidth : positive);
	port (A : in std_logic_vector (bitwidth-1 downto 0);
		 B : in std_logic_vector (3 downto 0);
		 Z : out std_logic_vector (bitwidth-1 downto 0)
		 );
end component;	

component audio_controller
	generic (bitwidth : positive; 
			loc_bitwidth : positive; 
			gain_bitwidth : positive; 
			delay_bitwidth : positive;  
			samples : positive 
	);
	port (
		system_clock : in std_logic;
		sample_clock : in std_logic;
		reset : in std_logic;
		Xloc : in std_logic_vector(loc_bitwidth-1 downto 0);
		Yloc : in std_logic_vector(loc_bitwidth-1 downto 0);
		Delay : out std_logic_vector(delay_bitwidth-1 downto 0);
		Gain : out std_logic_vector(gain_bitwidth-1 downto 0);
		Sample_Req : out std_logic;
		Data_Ready : in std_logic;
		Reg0_Load : out std_logic_vector(samples-1 downto 0);
		Reg0_Enable : out std_logic;
		Reg2_Load : out std_logic_vector(samples-1 downto 0);
		Reg2_Enable : out std_logic
		);
end component;

-- end component declarations.

-- begin signal declarations.

-- signals from audio_controller
signal Reg0_Enable : std_logic;
signal Reg2_Enable : std_logic;
signal Reg0_Load : std_logic_vector(samples-1 downto 0);
signal Reg2_Load : std_logic_vector(samples-1 downto 0);
signal Gain : std_logic_vector(gain_bitwidth-1 downto 0);

-- signals from Selectors
signal Reg0_Clock : std_logic_vector(regwidth-1 downto 0);
signal Reg2_Clock : std_logic_vector(regwidth-1 downto 0);

-- signals between registers
signal Reg0_0, Reg0_1, Reg0_2, Reg0_3 : std_logic_vector(bitwidth-1 downto 0);
signal Reg1_0, Reg1_1, Reg1_2, Reg1_3 : std_logic_vector(bitwidth-1 downto 0);
signal Reg2_0, Reg2_1, Reg2_2, Reg2_3 : std_logic_vector(bitwidth-1 downto 0);
signal Reg1_MUXOut, Gain_Out : std_logic_vector(bitwidth-1 downto 0);
-- end signal declarations.

begin

-- begin port maps.
Controller: audio_controller
	generic map (
		bitwidth => bitwidth,
		loc_bitwidth => loc_bitwidth,
		gain_bitwidth => gain_bitwidth,
		delay_bitwidth => delay_bitwidth,
		samples => samples
	)
	port map (
		system_clock => system_clock,
		sample_clock => sample_clock,
		reset => reset,
		Xloc => Xloc,
		Yloc => Yloc,
		Delay => Delay,
		Gain => Gain,
		Sample_Req => Sample_Req,
		Data_Ready => Data_Ready,
		Reg0_Load => Reg0_Load,
		Reg0_Enable => Reg0_Enable,
		Reg2_Load => Reg2_Load,
		Reg2_Enable => Reg2_Enable
);


Gain1: gain_mult
	generic map (bitwidth)
	port map (
	A => Reg1_MUXOut,
	B => Gain,
	Z => Gain_Out
);

Reg0_Selector: myselector2
	port map (
	I0 => Reg0_Clock(0),
	I1 => Reg0_Clock(1),
	I2 => Reg0_Clock(2),
	I3 => Reg0_Clock(3),
	Sel => Reg0_Load,
	SelectorIn => Reg0_Enable
);

Reg2_Selector: myselector2
	port map (
	I0 => Reg2_Clock(0),
	I1 => Reg2_Clock(1),
	I2 => Reg2_Clock(2),
	I3 => Reg2_Clock(3),
	Sel => Reg2_Load,
	SelectorIn => Reg2_Enable
);

Reg1_MUX0: mymux
	generic map (bitwidth)
	port map (
	I0 => Reg1_0,
	I1 => Reg1_1,
	I2 => Reg1_2,
	I3 => Reg1_3,
	Sel => Reg2_Load,
	MUXOut => Reg1_MUXOut
);	


Reg00: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg0_Clock(0),
	Reg_in => Sample_In,
	Reg_out => Reg0_0
);

Reg01: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg0_Clock(1),
	Reg_in => Sample_In,
	Reg_out => Reg0_1
);

Reg02: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg0_Clock(2),
	Reg_in => Sample_In,
	Reg_out => Reg0_2
);

Reg03: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg0_Clock(3),
	Reg_in => Sample_In,
	Reg_out => Reg0_3
);

Reg10: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg0_0,
	Reg_out => Reg1_0
);

Reg11: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg0_1,
	Reg_out => Reg1_1
);

Reg12: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg0_2,
	Reg_out => Reg1_2
);

Reg13: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg0_3,
	Reg_out => Reg1_3
);

Reg20: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg2_Clock(0),
	Reg_in => Gain_Out,
	Reg_out => Reg2_0
);

Reg21: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg2_Clock(1),
	Reg_in => Gain_Out,
	Reg_out => Reg2_1
);

Reg22: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg2_Clock(2),
	Reg_in => Gain_Out,
	Reg_out => Reg2_2
);

Reg23: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => Reg2_Clock(3),
	Reg_in => Gain_Out,
	Reg_out => Reg2_3
);

Reg_Speaker00: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg2_0,
	Reg_out => Speaker00
);

Reg_Speaker01: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg2_1,
	Reg_out => Speaker01
);

Reg_Speaker10: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg2_2,
	Reg_out => Speaker10
);

Reg_Speaker11: myregister
	generic map (bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => Reg2_3,
	Reg_out => Speaker11
);

end audio_manipulator;