-------------------------------------
--	audio_controller.vhd
--	Audio Controller
--
--	March 11, 2000
--	Ross, Daniel 355951
--	Status: 
--
--	This is the audio controller which
--	performs a variety of duties. This
--	controls everything in 
--	audio_manipulator.vhd.
--
--	INPUTS
--	=================================
--	System_clock, Sample_clock are 
--	our two clock signals. The Sample
--	clock is presumably at 44.1 KHz
--	and is produced by our ADC.
--	
--	Xloc, Yloc are the X and Y locations
--	of the sound. Both are 4-bit unsigned
--	integers.
--	
--	RAM Interfacing
--	=================================
--	We will ask RAM for samples off the
--	stack. We give our RAM interface the
--	Delay (a 5-bit unsigned integer) and
--	notify the interface with Sample_Req.
--	it will return a 24-bit sample (the
--	Delay*128'th sample down the stack)
--	tell us it's ready with a Data_Ready
--	signal. For each sample_clock rising edge,
--	we will retrieve eight samples from
--	RAM. (at the moment) and place each into
--	Registers Reg0_0 through Reg0_7. which we
--	control with an three-bit signal Reg0_Load.
--	
-- 	On each sample_clock rising edge, we load
--	Reg1_0 through Reg1_7 to provide stable data
--	for the gain multiplier. We use the one-bit
--	signal Reg1_Load to do this.
--	
--	Gain Control
--	=================================
--	We have a selector which we control with
--	GainIP_Select (3-bits) and a multiplier
--	A (a 4-bit unsigned integer) and pass to one
--	of eight registers Reg2_0 through Reg_7 using
--	an three-bit signal Reg2_Load.
--	
--	For each rising edge of the sample_clock, we
--	will sequentially gain-adjust each sample and
--	pass it on to the Reg2 registers.
--
--	Summing
--	=================================
--	for each speaker, we have produced a gain
--	-adjusted delay-adjusted incident sample and
--	a corresponding echo sample. Here, we add the
--	two signals together using four 24-bit adders.
--	outputted to registers Reg_speaker00 through
--	Reg_speaker11. This is outputted to the DAC.
--	


-- Use IEEE Libraries.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Declare entity. 

entity audio_controller is
	generic (bitwidth : positive := 16; -- 24 bit samples.
			loc_bitwidth : positive := 4; -- 4 bit location unsigned integers.
			gain_bitwidth : positive := 4; -- 4 bit gain unsigned integers.
			delay_bitwidth : positive := 5; -- delay is up to 31*128 =3968 
											-- samples (or .1 of a second.)
			samples : positive := 2 -- 2^2 = 4 samples per sample_clock period.
	);
	port (
		system_clock : in std_logic;
		sample_clock : in std_logic;
		reset : in std_logic;
		
		Xloc : in std_logic_vector(loc_bitwidth-1 downto 0);
		Yloc : in std_logic_vector(loc_bitwidth-1 downto 0);

		Delay : out std_logic_vector(delay_bitwidth-1 downto 0);
		Gain : out std_logic_vector(gain_bitwidth-1 downto 0);
		Sample_Req : out std_logic;
		Data_Ready : in std_logic;

		Reg0_Load : out std_logic_vector(samples-1 downto 0);
		Reg0_Enable : out std_logic;
		Reg2_Load : out std_logic_vector(samples-1 downto 0);
		Reg2_Enable : out std_logic
		);
end audio_controller;

architecture audio_controller of audio_controller is

-- component declarations follow.

component mymux
	generic (bitwidth : positive);
	port (I0, I1, I2, I3: in std_logic_vector(bitwidth-1 downto 0);
		  Sel : in std_logic_vector(1 downto 0);
		  MUXOut : out std_logic_vector(bitwidth-1 downto 0)
		);
end component;

component myregister
	generic (bitwidth : positive);
	port(reset, clock : in std_logic;
		 Reg_in : in std_logic_vector(bitwidth-1 downto 0);
		 Reg_out : out std_logic_vector(bitwidth-1 downto 0)
		);
end component;

component ac_gain_apply
	port (
			sample_clock : in std_logic;
			system_clock : in std_logic;
		
			reset : in std_logic;
			sample_select : out std_logic_vector(1 downto 0);
			reg2_enable : out std_logic
		);
end component;

component ac_get_samples
		port (
			sample_clock : in std_logic;
			system_clock : in std_logic;
		
			data_ready : in std_logic;
			reset : in std_logic;

			sample_req : out std_logic;
			reg0_load : out std_logic_vector(1 downto 0);
			reg0_enable : out std_logic
		);
end component;

component echo_delay
	generic (bitwidth : positive);
	port (X, Y : in std_logic_vector (bitwidth-1 downto 0);
		 T00,T01,T10,T11 : out std_logic_vector (bitwidth downto 0)
		);
end component;

component incident_gain
	generic (bitwidth : positive);
	port (X, Y : in std_logic_vector (bitwidth-1 downto 0);
		 A00,A01,A10,A11 : out std_logic_vector (bitwidth-1 downto 0)
		);
end component;

-- end component declarations.

-- begin signal declarations.

signal A00, A01, A10, A11 : std_logic_vector (gain_bitwidth-1 downto 0);
signal AConnect00, AConnect01, AConnect10, AConnect11 : std_logic_vector (gain_bitwidth-1 downto 0);
--signal ANull : std_logic_vector (gain_bitwidth-1 downto 0);

signal Reg0_LoadSignal : std_logic_vector (samples-1 downto 0);
signal Reg2_LoadSignal : std_logic_vector (samples-1 downto 0);

signal T00, T01, T10, T11 : std_logic_vector (delay_bitwidth-1 downto 0);
signal TNull : std_logic_vector (delay_bitwidth-1 downto 0);
signal TConnect00, TConnect01, TConnect10, TConnect11 : std_logic_vector (delay_bitwidth-1 downto 0);
signal Delay_SelectSignal : std_logic_vector (samples-1 downto 0);


-- end signal declarations.

begin

TNull <= "00000";
Reg2_Load <= Reg2_LoadSignal;
Reg0_Load <= Reg0_LoadSignal;

-- begin port maps.

Reg_A00: myregister
	generic map (gain_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => A00,
	Reg_out => AConnect00
);

Reg_A01: myregister
	generic map (gain_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => A01,
	Reg_out => AConnect01
);

Reg_A10: myregister
	generic map (gain_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => A10,
	Reg_out => AConnect10
);

Reg_A11: myregister
	generic map (gain_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => A11,
	Reg_out => AConnect11
);


Gain_MUX: mymux
	generic map (gain_bitwidth)
	port map (
	I0 => AConnect00,
	I1 => AConnect01,
	I2 => AConnect10,
	I3 => AConnect11,
	Sel => Reg2_LoadSignal,
	MUXOut => Gain
);	

Reg_T00: myregister
	generic map (delay_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => T00,
	Reg_out => TConnect00
);

Reg_T01: myregister
	generic map (delay_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => T01,
	Reg_out => TConnect01
);

Reg_T10: myregister
	generic map (delay_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => T10,
	Reg_out => TConnect10
);

Reg_T11: myregister
	generic map (delay_bitwidth)
	port map (
	reset => reset,
	clock => sample_clock,
	Reg_in => T11,
	Reg_out => TConnect11
);

Delay_MUX: mymux
	generic map (delay_bitwidth)
	port map (
	I0 => TConnect00,
	I1 => TConnect01,
	I2 => TConnect10,
	I3 => TConnect11,
	Sel => Reg0_LoadSignal,
	MUXOut => Delay
);	

incident_gain1: incident_gain
	generic map (gain_bitwidth)
	port map (
	X => Xloc,
	Y => Yloc,
	A00 => A00,
	A01 => A01,
	A10 => A10,
	A11 => A11
);

echo_delay1: echo_delay
	generic map (gain_bitwidth)
	port map (
	X => Xloc,
	Y => Yloc,
	T00 => T00,
	T01 => T01,
	T10 => T10,
	T11 => T11
);

ac_gain_apply1: ac_gain_apply
	port map (
	sample_clock => sample_clock,
	system_clock => system_clock,
	reset => reset,
	sample_select => Reg2_LoadSignal,
	reg2_enable => Reg2_Enable
);

ac_get_samples1: ac_get_samples
	port map (
	sample_clock => sample_clock,
	system_clock => system_clock,
	data_ready => Data_Ready,
	reset => reset,
	sample_req => Sample_Req,
	reg0_load => Reg0_LoadSignal,
	reg0_enable => Reg0_Enable
);

end audio_controller;