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-- AND
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library IEEE;
use IEEE.std_logic_1164.all;

entity and_2 is
    port (a    : in std_logic;
          b    : in std_logic;
          c : out std_logic);
end and_2;

architecture rtl of and_2 is

-- a simple adder with both carry in and carry out
-- without the use of "+" or an LPM
begin
    c <= a and b;
end rtl;