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-- An adder taken from my EE480 Class
-- Author	: Todd Carter	Jimmy Samuel
-- Student ID	: 355165	354837
-- Date	  	: January 28, 1999
-- File Name	: adder.vhd
-- Architecture	: RTL
-- Description	: 
-- Acknowledgements:
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library IEEE;
use IEEE.std_logic_1164.all;
entity adder is
    port (a    : in std_logic;
          b    : in std_logic;
          cin  : in std_logic;
          sum  : out std_logic;
          cout : out std_logic);
end adder;

architecture rtl of adder is

-- a simple adder with both carry in and carry out
-- without the use of "+" or an LPM
begin
    sum <= (a xor b) xor cin;
    cout <= (a and b) or (cin and a) or (cin and b);
end rtl;