------------------------------------------------- 
-- adc input controller
-------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
 
entity adc is
	port(clock			: in std_logic;
		 reset 			: in std_logic;
		 sample			: out std_logic_vector(23 downto 0); --SAMPLE_WIDTH-1
		 ack_in			: in std_logic;
		 ack_out		: out std_logic
		); 
end adc; 

architecture mixed of adc is 

signal state, next_state : std_logic_vector(1 downto 0);-- state_type
signal data_temp : std_logic_vector(24 downto 0);
signal s_data_temp :std_logic;
signal count : std_logic_vector(1 downto 0);
signal lr_side : std_logic;
signal data_count : std_logic_vector(4 downto 0);
signal start : std_logic;

begin 

adc_logic :process(clock,reset) 
begin
	if reset = '1' then
		next_state <= "00";--init
	else
		case state is
			-- initialize the state machine
			when "00"=> --init 
				ack_out <= '0';
				data_temp <= (others => '0');
				next_state <= "01";--waiting
	
			when "01"=> --waiting 
				next_state <= "10";--transfer
				data_temp <= "0010101010101010101010101";
				
			
			-- send data packet to system
			when "10"=>  --transfer
				sample <= data_temp(23 downto 0);
				ack_out <= '1';
				if ack_in = '1' then
					ack_out <= '0';
					next_state <=  "01";--waiting
				else
					next_state <=  "10";--transfer
				end if;
		
			when others =>
				next_state <= "00";--init
		end case;
	end if;
end process adc_logic;

state_register :process(clock) 
begin
	if rising_edge(clock) then 
			state <= next_state; 
		end if; 
end process state_register; 
end mixed;