-------------------------------------
--	ac_get_samples.vhd
--	Sample Retriever
--
--	March 11, 2000
--	Ross, Daniel 355951
--
--	This is a state machine that,
--	on the rising edge of the
--	sample clock, it will retrieve
--	8 24-bit samples from the
--	RAM Stack and place them in
--	Registers Reg0_0 through Reg0_7.
--

-- Use IEEE Libraries.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Entity Declaration.

entity ac_get_samples is
		port (
			sample_clock : in std_logic;
			system_clock : in std_logic;
		
			data_ready : in std_logic;
			reset : in std_logic;

			sample_req : out std_logic;
			reg0_load : out std_logic_vector(1 downto 0);
			reg0_enable : out std_logic
		);
end ac_get_samples;	

architecture behavioral of ac_get_samples is

-- Finite state machine states
type states is (idle, req_sample, get_data, increment, waitforlow, waitfordatanotready);
signal current_state, next_state : states;
signal n : std_logic_vector(1 downto 0);
signal sample_clock_in, data_ready_in : std_logic;

begin

combinational_logic : process (current_state, next_state, reset, sample_clock, system_clock)

begin

case current_state is
	when idle =>
					
		-- reg0_load <= "00";
		reg0_enable <= '0';
		sample_req <= '0';
						
		-- next state
		if sample_clock_in = '1' then
			next_state <= req_sample;
		else
			next_state <= idle;
		end if;

	when req_sample =>
		
	--	reg0_load <= n;
		reg0_enable <= '0';
		sample_req <= '1';

		-- next state				
		if reset = '1' then
			next_state <= idle;	
		elsif data_ready_in = '1' then
			next_state <= get_data;
		else
			next_state <= req_sample;
		end if;

	when get_data =>
		
	--	reg0_load <= n;
		reg0_enable <= '1';
		sample_req <= '0';

		-- next state. If n=3 then we go back to idle. 
		-- Otherwise, we increment n and go back to req_sample.
		if reset = '1' then
			next_state <= idle;
		elsif n < 3 then
			next_state <= waitfordatanotready;
		else
			next_state <= waitforlow;
		end if;

	when waitfordatanotready =>
	
	--	reg0_load <= n;
		reg0_enable <= '0';
		sample_req <= '0';

		-- next state
		if reset = '1' then
			next_state <= idle;	
		elsif data_ready_in = '0' then
			next_state <= increment;
		else
			next_state <= waitfordatanotready;
		end if;

	when increment =>

	--	reg0_load <= n;
		reg0_enable <= '0';
		sample_req <= '0';
		
		if reset = '1' then
			next_state <= idle;				
		else
			next_state <= req_sample;
		end if;

	when waitforlow =>
	
	--	reg0_load <= "00";
		reg0_enable <= '0';
		sample_req <= '0';
						
		-- next state
		if sample_clock_in = '0' then
			next_state <= idle;
		else
			next_state <= waitforlow;
		end if;
end case;

end process combinational_logic;

state_register : process(reset, system_clock, current_state) 
begin 
        if rising_edge(system_clock) then
			data_ready_in <= data_ready;
			sample_clock_in <= sample_clock;
		        -- advance to next state 
			current_state <= next_state;                
			if current_state = idle then
				n <= "00";
			elsif current_state = increment then
				n <= n+1;
			end if;
        end if; 
        
end process state_register; 

do_this : process(n)
begin

reg0_load <= n;

end process do_this;

end behavioral;