-------------------------------------
--	ac_gain_apply.vhd
--	Gain Apply State Machine
--
--	March 11, 2000
--	Ross, Daniel 355951
--
--	This is a state machine that,
--	on the rising edge of the
--	sample clock, it will multiply
--	four samples by four gain
--	coefficients.

-- Use IEEE Libraries.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Entity Declaration.

entity ac_gain_apply is
		port (
			sample_clock : in std_logic;
			system_clock : in std_logic;
		
			reset : in std_logic;
			sample_select : out std_logic_vector(1 downto 0);
			reg2_enable : out std_logic
		);
end ac_gain_apply;	

architecture behavioral of ac_gain_apply is

-- Finite state machine states
type states is (idle, do_gain, waitstate1, waitstate2, increment, waitforlow);
signal current_state, next_state : states;
signal n : std_logic_vector(1 downto 0);

begin

combinational_logic : process (current_state, next_state, reset, sample_clock, system_clock)

begin

case current_state is
	when idle =>

		reg2_enable <= '0';
						
		-- next state
		if sample_clock = '1' then
			next_state <= do_gain;
		else
			next_state <= idle;
		end if;
	
	when do_gain =>
	
		reg2_enable <= '1';
						
		-- next state
		if reset = '1' then
			next_state <= idle;				
		else
			next_state <= waitstate1;
		end if;

	when waitstate1 =>
	
		reg2_enable <= '1';

		-- next state
		if reset = '1' then
			next_state <= idle;				
		else
			next_state <= waitstate2;
		end if;


	when waitstate2 =>
		
		-- stop requesting sample.
		-- keep enable loading of reg0_n.

		reg2_enable <= '1';

		-- next state. If n=3 then we go back to idle. 
		-- Otherwise, we increment n and go back to req_sample.
		if reset = '1' then
			next_state <= idle;
		elsif n < 3 then
			next_state <= increment;
		else
			next_state <= waitforlow;
		end if;

	when increment =>

		reg2_enable <= '0';
						
		if reset = '1' then
			next_state <= idle;				
		else
			next_state <= do_gain;
		end if;

	when waitforlow =>
					
		reg2_enable <= '0';
						
		-- next state
		if sample_clock = '0' then
			next_state <= idle;
		else
			next_state <= waitforlow;
		end if;

end case;

end process combinational_logic;

state_register : process(reset, n, system_clock, current_state) 
begin 
        if rising_edge(system_clock) then
		        -- advance to next state 
                current_state <= next_state;                
			if current_state = idle then
				n <= "00";
			elsif current_state = increment then
				n <= n+1;
			end if;
	     end if; 
end process state_register; 

to_out : process(n)
begin

sample_select <= n;

end process to_out;

end behavioral;