-------------------------------------------------------------
-- A N bit Register
-- Author       : Marc Dowdell
-- Date         : February 24, 2000
-- Modified		: Travis Robinson March 30,2000
-- File Name    : receiver.vhd
-- Architecture : behavioral
-- Description  : The register inputs a serial bit stream and outputs
-- 	              a 7-bit word of our designation.
--   
-- Acknowledgements: A bit of help from Dr. Elliott.
-------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity receiver is
    generic(N : integer := 8); 
    port (	Input  : in std_logic;  -- This is the bitstream.
			Clock  : in std_logic;  -- This is our BCLKX input.
	  		Reset  : in std_logic;	-- This is our FSX clock
			Output : buffer std_logic_vector(N-2 downto 0));
end receiver;

architecture behavioural of receiver is

signal q:std_logic_vector(3 downto 0);
signal holder:std_logic_vector(N-1 downto 0); 
begin

	count :process(clock)
	begin
		if falling_edge(clock) then
			if reset = '0' then
				Output <= (others => '0');
				holder <= (others => '0');
				q <= "0000";
			elsif q = "1000" then
				Output <= holder(N-2 downto 0);  --we only want to read the last 7 bits.
			elsif reset = '1' then
				q <= q + '1';
				holder <= holder(N-2 downto 0) & Input;
			end if;
		end if;
				
	end process count;
	
end behavioural;