--------------------------------------------------
-- EE 552 Project, Automatic Volume Control
--
-- Mark Mielke, Mar 4, 2000
-- Revisions:
-- Travis Robinson, Mar 9,2000
-- Kreshka Niehaus, Mar 16,2000
-- Max, Min volume generator
-- Rev 3, Adding in the display
--
-- inputs are 4 buttons from user and clk:
--		one will select "maximum"
--		one will select "minimum"
--		one will increase value
--		one will decrease value
-- outputs are an 8-bit vector representing the Max Volume
-- and and 8-bit vector representing the Min Volume desired.
--
--------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

package avc_pack is

    component ssdisplay is
    generic(inwidth:positive:=4;
				outwidth:positive:=7);
	port(level:in std_logic_vector(inwidth-1 downto 0);
             seg1:out std_logic_vector(outwidth-1 downto 0));
    end component;

end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.avc_pack.all;

-- recal inputs from buttons will be active low.
entity max_min is
	port(
		rst, clk, max_sel, min_sel, incr, decr: in std_logic;
		max_vol, min_vol: buffer std_logic_vector(7 downto 0);
		count_out: out std_logic_vector(13 downto 0)
		);
end max_min;

architecture behaviour of max_min is

--split 8 bit binary number into 4s to convert to hex
signal upper_count_in,lower_count_in: std_logic_vector(3 downto 0);
signal upper_count_out,lower_count_out: std_logic_vector(6 downto 0);

signal max_val, min_val: std_logic_vector(7 downto 0);
signal allow_max_h, allow_max_l, allow_min_h, allow_min_l: std_logic;
signal max_val_incr,max_val_decr,min_val_incr,min_val_decr: std_logic_vector(7 downto 0);

signal diff,count_in: std_logic_vector(7 downto 0);

begin

-- the values of max_val and min_val will be between 7 and 0 and
-- 255 and 248 respectively and be in increments of 8.

incr_decr:process(incr,decr,rst)

begin
-- increment values created
if falling_edge(incr) then
	if max_sel = '0' and allow_max_h ='1' then 
		max_val_incr<=max_val+"00001000";
	elsif min_sel = '0' and allow_min_h = '1' then
		min_val_incr<=min_val+"00001000";
	end if;
end if;

-- decrement values created
if falling_edge(decr) then
	if max_sel = '0' and allow_max_l= '1' then
		max_val_decr<=max_val-"00001000";
	elsif min_sel='0' and allow_min_l = '1' then
		min_val_decr<=min_val-"00001000";
	end if;
end if;

end process incr_decr;

-- set max and min values at the clock edge
update:process(clk)
begin

if rising_edge(clk) then
	if rst ='0' then
		max_val<= "10011111";
		min_val<="10000000";
	elsif max_sel = '0' then
	    	
		if incr='0' then
			max_val<=max_val_incr;
		elsif decr='0' then
			max_val<=max_val_decr;
		end if;
		count_in<=max_val;
		
	elsif min_sel='0' then
		if incr='0' then
			min_val<=min_val_incr;
		elsif decr='0' then
			min_val<=min_val_decr;
		end if;
		count_in<=min_val;
	end if;
end if;

max_vol<=max_val;
min_vol<=min_val;

end process update;

		
check:process(max_val,min_val)

begin
	diff <= (max_val - min_val);

	-- min_val must be smaller than max_val
	if diff = "00000111" then
	  allow_max_l <= '0';
	  allow_min_h <= '0';
	else
		allow_max_l<= '1';
		allow_min_h<= '1';
	end if;

	--maximum value allowed
	if max_val = "11111111" then
	  allow_max_h <= '0';
	else 
		allow_max_h<= '1';
	end if;

	--minimum value allowed
	if min_val = "00000000" then
	  allow_min_l <= '0';
	else
		allow_min_l <= '1';
	end if;
end process check;

--split count_in into 4 bit segments
upper_count_in <= count_in(7 downto 4);
lower_count_in <= count_in(3 downto 0);


count_upper: ssdisplay port map(
	level => upper_count_in,
	seg1 => upper_count_out);

count_lower: ssdisplay port map(
	level => lower_count_in,
	seg1 => lower_count_out);

-- put count_out parts together with concatenation
count_out <= upper_count_out & lower_count_out;


end behaviour;