EE 552

Final Report

Automatic Volume Control

 March 15, 2000

 Travis Robinson, Marc Dowdell, Mark Mielke, Kreshka Niehaus

 (tgr@ee.ualberta.ca, mdowdell@ualberta.ca, mielke@ee.ualberta.ca, niehaus@ualberta.ca)

 

  

Declaration of Content

The project and the contents of this report are entirely the original work of the authors with the following exceptions:The following were printed from the various sources:

The CODEC chip circuit was printed from reference [1]

The CODEC operation diagram was printed from reference [1]

The OP-AMP chip pin assignment diagram was from reference [2]

The Pre-Amp chip pin assignment diagram was from reference [3]

 Otherwise the design was created independently.

The design of all architectures used [6] and [7] information as a rough template.

 Otherwise the architectures were all created independently by us.

 

Abstract

This document presents a detailed final report for one possible implementation of an "Automatic Volume Controller (AVC)". AVC is an accessory targeted to Walkmanâ and Discmanâ users. AVC is able to control the volume level of a pair of headphones, relative to the surrounding noise level. For example, when listening to an audio source in a quiet room, the volume does not have to be as loud in order to hear the music clearly. However, if one were to walk from that quiet room into a busy street, the increase in ambient noise might overwhelm the music. Likewise, when one walks into a quiet library, one might decide that the audio level is inappropriately loud. We propose to design a device that will detect these changes in ambient noise, and automatically change the headphone volume accordingly.

We have decided to simply amplify the levels coming out of the headphones. A feedback system that samples the output of the headphones would be a possible upgrade to this project at a later date. We believe at this time, that our design will fit on the Flex10K20 chip proposed earlier.

Table of Contents

Declaration of Content……………………………………………………………………………

Abstract

Table of Contents…………………………………………………………………………………

Achievements

Description of Operation

Description of FPGA I/O Signals

FPGA Design

Data Sheet……………………………………………………………………………………………

Logic Requirements

Results of Experiments…………………………………………………………………………

VHDL Code Index

References

Appendix

 

Achievements

The analog discrete components of our circuit are now working. This includes the microphone, the pre-amp for the microphone and the volume gain controller.

In addition all of our VHDL code is working. The code to receive the serial input stream of bits from the ADC successfully converts this stream to the 8-bit words representing the noise levels. The code to read these noise levels and integrate the signal to produce smoother level transitions is also working successfully. As far as functionality goes, the code that calculates the amount of signal amplification based on the noise level, and the max-min control with it, is also working. The top-level code brings all of these components together.

 Since our last report we have had to change our design slightly so we can use the TP3054B A/D converter chip rather than the one we had originally picked out, but the change over went smoothly. At the time of this report all of our VHDL code compiles and simulates perfectly. We have had some problems with the implementing of our whole circuit on the FPGA. We were able to implement all of the max/min, amplification calculation and display code and test that it was working properly on the board. At the moment however our top level design is not working as we had expected on the FPGA and as such we have a few problem to iron out before our presentations.

Description of Operation

The operation of the Automatic Volume Controller (AVC) is described below:

A mini-microphone is used to capture ambient acoustic noise surrounding the target user. Microphone output is amplified and then sampled by an analog to digital CODEC. The output digital bit stream from the CODEC is sent to the FPGA unit for signal processing.

The FPGA reads the output from the CODEC, and manipulates the data to obtain a smooth integrated value for the ambient noise level of the past three seconds, updating every second. From this level, and from a user-defined maximum and minimum volume level, the FPGA then determines the desired amplification power factor for the CD player’s headphone output.

The FPGA output of the desired amplification power factor then drives a selectable op-amp configuration, which is used to amplify the headphone noise level.

The FPGA will also drive 2 seven segment LED displays, which indicate the current level of amplification (from 00 to FF in hexadecimal), as well as the user defined maximum and minimum levels of amplification.

 

Figure 1 displays the block diagram of the AVC.

Figure 1: Automatic Volume Control Block Diagram

 

 

Block diagram component description

 A high level behavioral description of each component is discussed below.

 Microphone requirements:

One mini-microphone is responsible for capturing ambient acoustic noise from all directions. (RadioShack part # 270-085)

 Microphone pre-amplifier:

This unit is responsible for amplifying the microphone output to produce a usable signal. It must provide adequate signal strength to drive the Analog to Digital Converter. This device was built using an LM324 linear op-amp IC (RadioShack part # 2761711).

 Analog to Digital converter (ADC):

This device will sample the captured acoustic noise to produce a 24-bit data stream used by the FPGA unit. We will sample at a rate of 48 kHz, which is common in microphone devices and is the default rate of the CODEC chip used. (Texas Instruments part # TP3054B).

 Headphone amplifier:

This unit is responsible for driving a pair of headphones given a line level audio input. We may want to opt for an adjustable audio level potentiometer which will control the desired nominal gain of this amplifier. Two LM386s will be used. (RadioShack part # 276-1731).

 FPGA unit:

This device is responsible for detecting and analyzing the sampled data stream containing the ambient noise level information. The logic will:

 

Description of FPGA I/O signals

#/Signal/Pin Name I/O Logic level Function / Description

1/CLK/ I/ clock/ 25.175 MHz master clock

2/BCLKX/O/clock/25.175 MHZ/16 = 1.573MHZ

3/FSX/O/clock/fs = BCLKX/32 = 49.2 kHZ

4/RESET/I/active low/switch to reset FPGA

5/DX/I/Audio digital sample in.

6/MAX/I/active low/pushbutton to select maximum amp.

7/MIN/I/active low/pushbutton to select minimum amp.

8/UP/I/active low/pushbutton to increment max/min.

9/DOWN/I/active low/pushbutton to decrement max/min.

10-23/LED_1 to LED_14/O/active low/2 seven segment LED outputs.

24-31/AMP_0 to AMP_7/O/active low/amplification factor output.

Total signal pin numbers = 31

 

FPGA Design

 Figure 2 contains the diagram of the design hierarchy.

 

All elements of Figure 2 are architectures used in the FPGA.

Receiver: Receives the incoming serial bit stream, from the CODEC output, and converts the input to an 8-bit magnitude word.

Integrator: Sums 8 bit numbers.

Integrate_Count: Informs ‘Total_Integrator’ when each of 3 different integrators operate.

Total_Integrator: Calls ‘Integrate_count’ and runs Integrator accordingly. Integration done for three seconds, updated every second.

Noise_Out: Most Significant 8 bits of the ‘Total_Integrator’.

Max_Min: Inputted maximum and minimum amplification values inputted from User, and displays it on the 7 segment LEDs.

Amplification: Evaluates from Max, Min and Noise what amplification factor will be.

Amp_Display: Display algorithm for amplification amount.

SsDisplay: Converts an 8 bit binary number into a value between 0 and FF for an O/P display of 2 seven segment LEDs.

A.V.C. Data Sheet

General Description

The Automatic Volume Controller or A.V.C. is a sound system accessory that is targeted towards portable music players such as a Walkmanâ , Discmanâ , or MPEG-type player. When using one of these devices in an environment where the volume of the noise in the surroundings is constantly changing, one often finds it necessary to constantly adjust the headphone volume output to reflect these changes, which can be a bother. The function of the AVC is to make such volume adjustments automatic.

The AVC accomplishes this task by first taking in an analog input from a microphone. This input represents a sample of the ambient noise in the surroundings. This signal is then amplified and fed into an analog to digital converter (ADC) as the computational functions of the AVC will be performed in digital logic. The resulting digital output from the ADC is then fed into the FPGA, the Altera EPF10K20RC240-4, where it will be used to compute a suitable output volume level. Additionally, there are two other inputs to the FPGA. These consist of user-specified maximum and minimum volume levels by means of maximum and minimum select buttons and increment and decrement buttons. The user can modify these values by simply selecting the maximum or minimum, then using the increment/decrement buttons. The output of the FPGA, a digital logic vector, is then sent to the gain controller. The gain controller also takes an input of a two-wire output from a music player. Based on the output from the FPGA, the gain controller then amplifies the music signal be the desired amount.

Specifications

---- Power Requirements:

Supply voltage to FPGA: – 9V DC

Current drawn by FPGA: – 200 mA.

Supply voltage to amplifier: – +/- 5V

Supply voltage to ADC: – +/- 5V

Current drawn by amplifier and ADC: – 11mA

Supply voltage to gain controller: – 6 V

Current drawn by gain controller: – 4mA

---- Clock Frequency Requirements:

Main FPGA clock frequency: – 25.175MHz

ADC clock frequency: –1.573MHz

ADC Sampling Frequency:– 49.2kHz

---- ADC Specifications:

ADC max per conversion time: – 0.9 ms

---- Logic Requirements:

Total logic cells: – 736 (63%)

--See IOlist.html for our list of I/O Pins.--

Logic Requirements

The Report created with the ‘AVC_controller’ compiled stated that it used 736 logic cells of the possible 1152 cells (63%) in the FPGA. Of these the largest number came from the ‘total_integrator’ which used 297 cells (25%), followed by ‘max_min’ with 237 logic cells (20%) and ‘amp_calc’ with 137 (11%). As can be seen from these results, space is not a problem for our design and we would be able to implement feedback at a later date if we so desired. The timing analyzer showed that the registered performance of our program is: Clock Period: 118.4ns, Frequency: 8.44MHz. This is faster than the clocks we require so timing was not an issue.

Results of Experiments

One of the things that we experimented with in the course of our design was the number of logic blocks used to implement an architecture using different types of synthesis. We found that by using fast rather than normal synthesis for the top level of our design we were able to reduce the number of logic blocks used from 736 of 63% to 689 or 59%. This would have been particularly useful if our design was close to filling the chip.

Another thing that we tried was experimenting with speed vs. area trade-offs. We found that when we optimized area and used fast synthesis we used 689 logic blocks (59%), but when we optimized speed using fast synthesis we needed 718 logic block (62%).

 

 VHDL Code Index

Receiver: The code that receives the serial input of bits from the ADC and converts this into the 8-bit words for our integration code.

Integrate_count: The code that keeps track of the three concurrent integrations.

Integrator: The code that integrates our sampled data.

Total_Integrator: The top level integrator code, incorporating all three concurrent integrators.

Noise_out: The algorithm used to calculate our integration factor from our integration results.

Max_min: The code that takes the user inputs for desired maximum and minimum volume levels and displays these on the seven segment LED’s in hex form.

Amp_calc: The code that takes the noise_out input and max-min volume levels and outputs as well as displays the appropriate amplification level.

Master_clock: Divides internal clock by 1152 to give a sampling frequency of 49.17kHz.

AVC_controller: The top-level code that brings all the architectures together.

References

Appendix

 Includes: