VHDL Descriptions 2. Receiver entities Entity: rec2.vhd Purpose: top level receiver entity . Function: The input to this entity is serial data from the FM receiver. Data is stored and decoded. The decoded data is displayed on LEDS and on a 7 segments display. A VGA monitor is used to display static data including the sensors output. Logic Cells Required: 763/1152 Entity: patterndetector.vhd Purpose: Detects the pattern "552" and signals the starting of reception. Function: This entity checks the incoming data from the FM receiver for the pattern "552". Once this pattern is detected, this entity sets a flag high "match". This flag remais high for the duration of 48 bits. Logic Cells Required: 141/1152 Entity: buff.vhd Purpose: Stores 48 bits. Function: This entity accept 48 bits of serial data as long as the flag "match" is set high. The output of the entity is a 48 bits word components used: reg.vhd (generic shift left register) Logic Cells Required: 49/1152 Entity: er_det.vhd Purpose: detects errors in the incoming data. Function: This entity checks the incoming data. If the pattern"1111" is detected at a specified location in each 12 bits word, the word is stored in a 12 bits latch. Otherwise, the 12 bit latch for this word is not updated. components used: lat.vhd (generic latch) Logic Cells Required: 100/1152 Entity: myvhds.vhd Purpose: displays static data on the VGA monitor. Function: This entity checks displays static data representing sensors on the VGA monitor. Logic Cells Required: 303/1152 Entity: multiplex.vhd Purpose: this entity is used to test raw data. Function: This entity checks the data before it is sent to the data decoder. A push button increments the content of a counter. Each counter value corresponds to the contents of a latch. Data from each latch can be presented on the 7 segments display. Logic Cells Required: 36/1152 Entity: button.vhd Purpose: this entity is used to test raw data. Function: A push button is used to increment a counter, the output of this counter is connected to the entity multiplex.vhd Logic Cells Required: 18/1152 Entity: div8.vhd.vhd Purpose: this entity divides the input clock. Function: scales down the input clock from 25.175 Mhz to 12.3 Khz. components used: toggle.vhd Logic Cells Required: 11/1152 Entity: d.vhd Purpose: D flip flop Function: synchronizes the input data to the receiver. Logic Cells Required: 1/1152 Entity: toptest.vhd Purpose: test the receiver for correct operation. The VGA driver and data decoder are not tested by this entity.