Achievements
The Vox-o-Tron’s internal digital circuitry behaves as intended. The inputs from the ADC (analogue to digital converter) are convolved and output to the DAC (digital to analogue converter). Unfortunately, the noise inherent in the physical implementation of the support circuitry makes the device unusable.
In terms of processing, the Vox-o-Tron is able to support a sampling rate of 48kHz, but using a FLEX10K20 FPGA, can only accommodate 8 bit processing. Using the same grade of chip with a higher gate count, 24 bit processing would be possible at this rate. In fact, the system is clocked such that the sampling rate is 49.1kHz, which is within tolerances of the ADC (the DAC has no problem with very high sampling rates).
I/O Description
The Vox-o-tron has two analogue audio inputs and one analogue audio output. The fist input is known as the exciter input. The second input is referred to as the carrier signal. These inputs usually consist of a voice and a synthesizer respectively. Optionally, another audio output could be added, as well as a frequency shifting controls. The additional output could be used to monitor a clean or frequency shifted exciter signal. Frequency shifting controls could be used to modify the base frequencies in the exciter signal. Also, a VGA monitor output could be integrated into the system to display the frequency spectrum of the voice input.
General Description of Operation
The operation of a musical vocoder in general is as follows. The exciter signal has its frequency spectrum imposed on the carrier signal. In musical vocoders, this is done approximately. Most of these devices are analogue, and use an array of discrete bands in the frequency range of human speech to control a corresponding array of band-pass filters (BPF’s) which act on the carrier signal. In a digital system, it is possible to do the same except with many more frequency bands by convolving the carrier signal with the exciter signal.
Rather than approximate the frequency spectrum of the exciter signal to filter the carrier signal, they are convolved together, thereby multiplying the frequency spectrums together. The exciter signal is connected to the left channel of the stereo A/D converter (CS5360). The carrier signal is connected to the right channel of the CS5360. These signals are sampled at 49.1 kHz. Both of the resulting digital signals pass through an audio signal decoder, which converts the serial data (which is in the I2S format described in the CS5360 documentation, attached) into two parallel 8-bit data streams. The data coming in has 24 bits per channel, but only the most significant 8 bits are used to reduce the size of the processing hardware. The signals are stored in two 128-value (in this case, 128 byte) buffers comprised of the on-chip SRAM cells. Every time a new sample is stored, the buffers are immediately convolved. The result of the convolution is output to the DAC interface, which converts the single 8 bit parallel data into an I2S data stream (described in the CS4334 documentation, attached).
Convolver
Operation
The convolving is done using a method developed by the team based on the FIR filtering techniques described in references #2, #5, and #6. Convolution of two discrete-time filters is accomplished by multiplying the two signals together, coefficient by coefficient, then summing all the resultant values. The convolver accesses all of the values stored in the buffer, feeding them into a pipelined multiplier. The result of each operation is a 16 bit number. An adder sums the values coming out of the multiplier, then truncates this value to the last 7 bits, preceded by the sign bit.
Figure 1: Block Schematic of Vox-o-Tron
Input Decoder
The input decoder converts the serial data from the A/D converter into two parallel data streams. It effectively separates the left and right channel information and produces two standard logic vectors. This is done by shifting the incoming bits through a 64-bit shift register. The resulting vector contains, in sequence, a 24-bit value representing the current left channel sample, 8 bits representing a peak signal level detection value for the left channel, a 24-bit value representing the current right channel sample, and 8 bits representing a peak signal level detection value for the right channel. Eight bits of data from the left and right channels can be read from bits 63 down to 56, and 31 down to 24, respectively. This data is latched at the end of the cycle. See crystal data sheets [1].
Circular Buffer
The circular buffer allows one to continually add values to RAM and read them in order of newest to oldest (LIFO: Last In, First Out).
FIR Unit (Convolver)
This block must perform convolution on a signal based upon a filter's impulse response. In this case, the exciter signal will be convolved directly with the carrier signal. To accomplish this, the coefficients of the incoming audio data buffers must all be multiplied together then summed. This means that the data must be fetched from the circular buffers as many times as there are elements in the buffers. In this case, 128 times.
DAC Interface
The DAC interface performs the opposite function as the ADC interface. It converts parallel data into serial data. This is performed by latching the parallel data into a shift register (of which the most significant bit is mapped to the serial output, sdata). The data is then shifted out on the sdata clock. See crystal data sheets [2].
IO Signals
External IO:
Note: all IO signals for the Vox-o-Tron are analogue.
|
IO Signal |
Type |
Source |
Destination |
|
Exciter input |
Line level monophonic analogue audio. |
Any audio source. Typically voice. |
CS5360 ADC |
|
Carrier input |
Line level monophonic analogue audio. |
Any audio source. Typically audio from a synthesizer |
CS5360 ADC |
|
Master output |
Line level monophonic analogue audio. |
CS4334 DAC |
Audio source, mixer, etc. |
Internal IO:
|
IO Signal |
Type |
Source |
Destination |
|
serialAudioInput |
Input to FPGA: I2S format (from CS5360 documentation). Contains left and right channel data, and peak signal level (PSL) detection bits. |
CS5360 ADC (pin 9) |
Pin 23 on the FLEX_EXPAN_A port of the UP1 education board (fitted with a FLEX10K20RC240-4 FPGA) |
|
lrclk |
Input to FPGA: 50% duty cycle clock at the sampling frequency of the ADC. |
CS5360 ADC (pin 12) |
Pin 24 on the FLEX_EXPAN_A port |
|
sclk |
Input to FPGA: 50% duty cycle clock at 64X the sampling frequency. |
CS5360 ADC (pin 8) |
Pin 22 on the FLEX_EXPAN_A port |
|
reset |
Input to FPGA: pushbutton signal |
PB1 on the UP1 board |
Pin 28 of the FLEX10K20 chip |
|
chipReset |
Output from FPGA: active low reset signal. |
Pin 18 on the FLEX_EXPAN_A port |
CS5360 ADC (pin 18) |
|
serialAudioOutput |
Output from FPGA: I2S format (from CS4334 documentation). Contains left and right channel. |
Pin 15 on the FLEX_EXPAN_A port |
CS4334 DAC (pin 1) |
|
lrclkOut |
Output from FPGA: 50% duty cycle clock at the sampling frequency |
Pin 16 on the FLEX_EXPAN_A port |
CS4334 DAC (pin 3) |
|
mclk, mclk2 |
Output from FPGA: clocks at 256X the desired sampling frequency |
For mclk: pin 17 on FLEX_EXPAN_A For mclk2: pin 21 on FLEX_EXPAN_A |
For mclk: pin 4 on the CS5360 For mclk2: pin 7 on the CS4334 |
Note: mclk and mclk2 are separated to allow for alternate designs to use different master clock speeds for the ADC and DAC.
Design Hierarchy
Vox-o-tron (main
structure) 3
3 3 x x
3
3
Fig. 2: Design Hierarchy
Resource Usage
Input Decoder (A/D Converter Interface)
From the compilation report, the decoder uses 104 logic cells on a FLEX10K20RC240-4 chip.
Output Encoder (D/A Converter Interface)
The output encoder uses up 34 logic cells.
FIR Unit (Convolver)
The compilation report states that the convolver uses 394 logic cells.
In total, Vox-o-tron’s VHDL code uses up 511 of the available 1152 cells (using 8 bit processing).
Experiment Results (Design Considerations)
Convolver
The convolver needs to multiply and add. Adders are not difficult to implement (particularly simple ripple-carry adders). The size of a multiplier as implemented by lpm_mult goes up exponentially with the data width. As an initial test, a 20-bit multiplier was compiled by Max+plus II. The resulting design required 1259 logic units. This is over 100 more logic units than are present in a FLEX10K20. Instead of using a larger device, the data width was cut down to 8 bits. This resulted in a multiplier which takes up roughly 30% of the capacity of the FLEX10K20.
For testing purposes, the 20-bit multiplier was benchmarked to see how much processing can occur in one audio clock cycle. The limiting factor in the speed of the convolver is how fast the multiplier can output data. The fastest an lpm_mult can go is when it is set to calculate in four pipeline stages (according to the Max+plus II online help). Thus, the registered performance of a 20-bit lpm_mult was tested using Max+plus II’s registered performance analysis tool. With constant data coming in, the multiplier can output 128 products in one cycle of a 56kHz clock. Given that the target sampling rate was set to 48kHz, the actual calculations were proved to not be an issue. Any additional latency comes from any setup of the convolving process and post-processing.
After compiling the FIR unit (which ties the convolver to the input buffers), it was found that the maximum sampling rate would be approximately 52kHz, which is still faster than the target sampling rate.
ADC Mode / Clocking
The ADC was set to operate in master mode, format 0 (specifications included in CS5360 documentation, attached). In this mode, a master clock (MCLK) is sent to the ADC, and it generates an LRCLK (left/right clock: runs at the sampling frequency), and an SCLK (serial clock), which are externalized. MCLK must run at 256X the desired sampling rate. Starting off with an 48kHz sampling frequency, this means MCLK must run at 12.288MHz, which is the UP1 board’s 25.175MHz clock divided by 2.049. The closest integer divider is 2, giving an MCLK running at 12.5875MHz. This corresponds to a sampling rate of 49.1kHz, which the ADC is able to handle.
This ADC features peak signal level detection. This is a powerful feature of high resolution ADCs which is completely ignored for the sake of this project.
DAC Mode
The DAC is put into Base Rate Mode (BRM) by providing an MCLK and LRCLK to it where the ratio of MCLK/LRCLK is 256. Also, it is set to internal SCLK mode by setting the (not DEM)/SCLK line to low logic level. After a few transitions of MCLK, the DAC realizes it must generate its own SCLK. Also, this setting turns on digital de-emphasis, which eliminates imaging. In this mode, the DAC converts 16 bits per channel and is able to reach ridiculously high sample rates. Here, the LRCLK generated by the ADC is fed into the DAC (buffered by the FLEX10K20). No SCLK is necessary, as it is generated internally. However, SDATA (the serial data stream fed to the DAC) must be clocked on a synchronized SCLK. The SCLK used to do this comes from the ADC.
Component Layout
The analogue signal lines are very sensitive to the 5-Volt digital lines. Unfortunately, these were not isolated adequately in Vox-o-Tron, resulting in crippling noise on the ADC analogue inputs. This was compounded by the fact that all wiring was done with thin wire-wrap wire. Also, it is possible that the pins soldered to the board containing the surface-mount chips (both the DAC and ADC) were too long and close together, resulting in antenna-like interference.
References
1.Crystal Semiconductors, Crystal Semiconductors, www.crystal.com
ADC CS5360, http://www.cirrus.com/products/overviews/cs5360.html
DAC CS4334, http://www.cirrus.com/products/overviews/cs4334.html
2. Student Application Notes (Winter 99) on FIR filters, Norman Bo, Kelvin Leung, David Ritter, www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/99w/FIRFilter/
3. Sampling and Filtering, Michael Cohen, screwdriver.bu.edu/cn760-lectures/l3/l3np/ppframe.htm
4. How Vocoders Work, Craig Anderson, www.paia.com/vocodwrk.htm
5. Kraftwerk info, http://sun1.bham.ac.uk/busbykg/kraftwerk/FAQ/miscellaneous.html#vocoder
Schematics / Connection information
Fig. 3: CS5360 Connections (ADC)
Page 8 CS5360 Appendix A
Fig. 4: CS4334 Connections (DAC)
Page 10 CS4334 Appendix B
Chip
Settings: ADC
Pin 1 (High-Pass Filter defeat) – connected to a low logic level to enable the high-pass filter.
Pin 2 – Overflow. Unused, so connected to ground through a 47kOhm resistor.
Pin 10 – Connected to ground through a 47kOhm resistor (ignored).
Pin 11 – Peak Update. Tied to ground to disable feature.
Pins 19, 20 – Both connected to logic level low to select data format 0.
Chip
Settings: DAC
Pin 2 – Digital De-Emphasis is turned on.
Pins 3, 4 – The incoming ratio of MCLK/LRCLK puts the DAC in master mode. It then provides its own SCLK and runs in 16 bit per channel mode.
Index to Test Cases / Verification
ADC Interface
Two different sdata sequences were tested. When lrclk = ‘1’ outputA and outputB are generated. OutputA and OutputB correspond to the sdata (7 downto 0) and sdata (40 downto 32), respectively.
DAC Interface
1. The binary values for 1 through 9 are converted to serial representations.
2. Hexadecimal values (shown in hex for easy conversion to binary) FB through FF are converted to their serial representations.
Circular Buffer
The integer value 3 is written to the buffer. The buffer is then read from twice. Next, the integer value 2 is written to the buffer. Lastly, it is read from three times. The values retrieved from the buffer are shown to be correct.
Convolver
1. All values in both buffers are simulated to be ‘1.’ This should 1 to the sum 128 times.
2. All values in buffer A are 1, all values in B are 3. This will repeatedly add 3 to the sum.
3. This is a two’s compliment test. Buffer A contains all –3’s, buffer B contains all 2’s.
4. Buffer B contains all 2’s (for simplicity) and buffer B contains values from 0 incrementing by 1 for each value (as if values 0, 1, 2, 3, etc. were received in that order).
FIR Unit
This test simulates a full clock cycle, and the beginning of a second. Two values are ‘received’ from the ADC on channels A and B: 2 and 3, respectively. On the beginning of the next cycle, a 3 and a 2 are received. This means that the circular buffers A and B contain {2, 0, 0, …} and {3, 0, 0, …}, respectively for the first cycle, and {2 ,3 ,0 ,…} and {3, 2, 0, …} respectively for the second. The output is then observed.