-------------------------------------------------------------------------------
-- File: shift8bitreg.vhd
--
-- Project: Porta-AMP (MP3 player)
-- Created by: Daniel Leder
-- Date: 10/30/99
--
-- Purpose: to shift out the msb of a register and shiftin a zero.
--
-- Inputs:
--
-- Outputs:
--
-- External Connections:
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mp3_decode_pkg.all;

entity shift8bitreg is
	generic (regwidth : positive := 8);
	port (data : in std_logic_vector(regwidth-1 downto 0);
		clock, reset, load : in std_logic;
--		shiftin: in std_logic;
		done: buffer std_logic;
		msb, empty: out std_logic
	);
end shift8bitreg;

architecture behaviour of shift8bitreg is

	signal count : std_logic_vector(4 downto 0);
	signal contents : std_logic_vector(regwidth-1 downto 0);
	signal regempty : std_logic;

begin

	empty <= regempty or reset;

	with count select
		regempty <=
			'1' when "10000",	-- 16
--			'1' when "01000",	-- 8
			'0' when others;	

	shiftbit: process (clock, load)
	begin
		if load = '1' then
			contents <= data;
			done <= '1';
		elsif rising_edge(clock) then
			done <= '0';
			msb <= contents(regwidth-1);
			contents <= contents(regwidth-2 downto 0) & '0';
--			msb <= contents(0);
--			contents <= '0' & contents(regwidth-1 downto 1);
		end if;
	end process shiftbit;

	recordcount: process (clock, load)
	begin
		if load = '1' then
			count <= (others => '0');
		elsif falling_edge(clock) then
			count <= count + '1';
		end if;
	end process recordcount;			
end behaviour;