-- CMPE498 Interfacing SDRAM to a microprocessor
-- file: sdram_package.vhd
-- Author: Kevin Mlazgar

-- Revision 1.1
-- Added all required components...

-- Revision 1.0  1999/07/25
-- initial revision.
--

-- A package of all the files used in the SDRAM interface project.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 

package sdram_package is


component d_ff is -- a dff
	port (
	-- Clock
	clk : in std_logic;
	-- Clock enable
	clk_en : in std_logic;
	-- synchronous clear
	clr : in std_logic;
	-- D input
	d : in std_logic;
	-- Q output
	q : buffer std_logic
	);
end component d_ff;


component synchronizer is -- a couple dffs
	port (
	-- Clock
	clk : in std_logic;
	-- D input
	async : in std_logic;
	-- Q output
	insync : buffer std_logic
	);
end component synchronizer;


component generic_register is
	generic (
	-- width for parameterized register...
	generic_register_width : integer := 16
	);
	port (
	-- Clear
	generic_register_clr : in std_logic;
	-- Clock enable
	generic_register_clk_enable : in std_logic;
	-- Clock
	generic_register_clk : in std_logic;
	-- D inputs
	generic_register_d : in 
		std_logic_vector(generic_register_width-1 downto 0);
	-- Q outputs, USED ONLY AS OUTPUTS...
	generic_register_q : out
		std_logic_vector(generic_register_width-1 downto 0)
	);
end component generic_register;

component tristate_buffer is
	port (
	-- output enable line
	enable : in std_logic;
	-- unbuffered input
	input : in std_logic;
	-- output
	output : out std_logic
	);
end component tristate_buffer;

component generic_register_with_oe is
	generic (
	-- width for parameterized register...
	generic_register_width : integer := 16
	);
	port (
	-- Output enable
	generic_register_oe : in std_logic;
	-- Clear
	generic_register_clr : in std_logic;
	-- Clock enable
	generic_register_clk_enable : in std_logic;
	-- Clock
	generic_register_clk : in std_logic;
	-- D inputs
	generic_register_d : in 
		std_logic_vector(generic_register_width-1 downto 0);
	-- Q outputs, USED ONLY AS OUTPUTS...
	generic_register_q : inout
		std_logic_vector(generic_register_width-1 downto 0)
	);
end component generic_register_with_oe;


component csadder is
	generic (
	-- width of adder
	datawidth : positive := 12
	);
	port(adden1, adden2, adden3 : 
			in std_logic_vector(datawidth-1 downto 0);
		sum_part1, sum_part2 : 
			buffer std_logic_vector(datawidth downto 0)
--		sum_unified : 
--			buffer std_logic_vector(datawidth downto 0)
	);
end component csadder;


component cscounter is
	generic (
	-- width of counter
	datawidth : positive := 12
	);
	port (
		clock, sreset : in std_logic;
		-- the following is only used during testing
		count_unified : out std_logic_vector(datawidth-1 downto 0);
		-- Output is in two binary weighted vectors which can be added to
		--  obtain the unified count.
		-- Following two lines used if we do not exceed
		--  the pin count of the device.
		count_part1_out, count_part2_out
			: buffer std_logic_vector(datawidth-1 downto 0)
	);
end component cscounter;


component constant_timer is
	generic (
	-- width for parameterized counter, and comparator...
	-- *** Can choose smallest optimal width depending on frequency of
	--		operation.
	-- To obtain a 0.5us period we can operate at 1/(0.5us/2^5) = 64Mhz
	-- with the default width of 5. See actual entity for specifics...
	constant_timer_width : integer := 5
	);
	port (
		-- initialize count
		constant_timer_clr_count : in std_logic;
		-- Clock
		constant_timer_clk : in std_logic;
		-- constant signal input1
		constant_timer_value1 : in std_logic_vector(constant_timer_width-1 downto 0);
		-- constant signal input2
		constant_timer_value2 : in std_logic_vector(constant_timer_width-1 downto 0);
		-- Active high line which indicates that the period of
		-- the timer has passed. Only lasts one clock cycle then
		-- count restarts...
		constant_timer_period_elapsed : out std_logic
	);
end component constant_timer;


component ff_behave is
    port (
		-- clock
		ff_behave_clk : in std_logic;
		-- reset
		ff_behave_reset : in std_logic;

		-- clear the latched value (somewhat redundant w/ the reset)
		ff_behave_clr : in std_logic;

		-- Active high line which must last at least one rising edge
		-- of the clock cycle...
		ff_behave_set : in std_logic;

		-- latched output
		ff_behave_q : out std_logic
	);
end component ff_behave;


component cpu_int_cont is
    port (
	-- clock
	cpu_int_cont_clk : in std_logic;

	-- reset
	cpu_int_cont_reset : in std_logic;

	-- ******************************
	-- ** Primary Datapath Signals **

	-- signal indicating that upper/lower address registers should
	--  load the address
	dpath_addr_bits_load : out std_logic;

	-- signal indicating that cpu is issuing a write
	dpath_cpu_write : in std_logic;

	-- signal indicating that write_data register should load write value
	dpath_write_data_load : out std_logic;

	-- signal indicating that cpu is issuing a read
	dpath_cpu_read : in std_logic;

	-- ************************
	-- ** CPU Direct Signals **

	-- signal indicating that sdram is ready for an access
	-- initializes to being ACTIVE (HIGH), during an access it will
	--  go low before going high again to indicate valid read data.
	cpu_int_ready : out std_logic;

	-- ********************************
	-- ** Primary Controller Signals **

	-- handshaking signals to SDRAM controller
	pcont_read_issue : out std_logic;
	pcont_write_issue : out std_logic;

	-- ack occurs after pcont has RXed a read or write
	pcont_ack : in std_logic;

	-- done occurs after pcont has finished servicing a read or write
	pcont_sdram_done : in std_logic

	);
end component cpu_int_cont;


component primary_cont is
    port (
	-- clock
	primary_cont_clk : in std_logic;

	-- reset
	primary_cont_reset : in std_logic;

	-- **************************************
	-- ** CPU Interface Controller Signals **

	-- handshaking signals from cpu int controller
	cint_read_issue : in std_logic;
	cint_write_issue : in std_logic;
	cint_ack : out std_logic;

	-- done occurs after pcont has finished servicing a read or write
	cint_sdram_done : out std_logic;

	-- **************************
	-- ** SDRAM Direct Signals **

	-- Command code outputs to sdram, defining sdram operations
	-- See p.10 of Micron 8,16 MEG x 64 SDRAM DIMMs data sheet
	-- for the complete truth table...
	sdram_rasn : out std_logic;
	sdram_casn : out std_logic;
	sdram_wen : out std_logic;

	-- SDRAM clock enable to CKE0 and CKE1
	-- used to implement self refresh
	--sdram_cke : out std_logic;

	-- SDRAM chip selects for 64 MB and 128MB DIMMs
	sdram_s0n : out std_logic;
	sdram_s2n : out std_logic;

	-- SDRAM chip selects for 128 MB DIMM only
	sdram_s1n : out std_logic;
	sdram_s3n : out std_logic;

	-- ************************
	-- ** CPU Direct Signals **


	-- ******************************
	-- ** Primary Datapath Signals **

	-- chip select address from address upper bit register
	-- Considered part of command code
	dpath_chip_sel_addr : in std_logic_vector(1 downto 0);

	-- read_data register clock enable on sdram_primary_datapath
	dpath_read_data_load : out std_logic;

	-- write_data register output enable on sdram_primary_datapath
	dpath_write_data_oe : out std_logic;
	
	-- mux select, which of two internal signals to drive
	-- sdram_address:
	-- 00 OR 01 the decoded row_bank_cs
	-- 10 the decoded col_dqmb_cmd
	-- 11 the load mode register value which exists in the primary data path
	dpath_address_select : out std_logic_vector(1 downto 0)
	);
end component primary_cont;


component primary_datapath is
	port (
	-- Clock
	primary_datapath_clk : in std_logic;

	-- **************************************
	-- ** CPU INTERFACE CONTROLLER Signals **

	-- signal indicating that upper/lower address registers should
	--  load the address
	cint_addr_bits_load : in std_logic;

	-- signal indicating that cpu is issuing a write
	cint_cpu_write : out std_logic;

	-- signal indicating that write_data register should load write value
	cint_write_data_load : in std_logic;

	-- signal indicating that cpu is issuing a read
	cint_cpu_read : out std_logic;

	-- ********************************
	-- ** SDRAM CONTROLLER Signals **

	-- read_data register clock enable on sdram_primary_datapath
	pcont_read_data_load : in std_logic;

	-- write_data register output enable on sdram_primary_datapath
	pcont_write_data_oe : in std_logic;
	
	-- mux select, which of two internal signals to drive
	-- sdram_address:
	-- 00 OR 01 the row_addr
	-- 10 the column_prchrg_addr
	-- 11 the load mode register value
	pcont_address_select : in std_logic_vector(1 downto 0);

	-- chip select address from row_bank_cs register
	-- Considered part of command code
	pcont_chip_sel_addr : out std_logic_vector(1 downto 0);

	-- ************************
	-- ** CPU DIRECT Signals **

	-- when '0' indicates that cpu will be providing address to
	--	address registers
	-- when '1' indicates that cpu will be issuing a read or a write to
	--	the address held in the address registers
--	cpu_command : in std_logic;

	-- cpu active-low Chip Select signal is asserted when cpu is addressing
	-- SDRAM controller
	cpu_csn : in std_logic;

	-- cpu read/writen line
	--  '1' indicates a READ
	--  '0' indicates a WRITE
	cpu_r_w : in std_logic;

	-- cpu output enable line
	cpu_oen : in std_logic;

	-- cpu enable byte0
--	cpu_eb0n : in std_logic; -- upper byte [15:8]

	-- cpu enable byte1
--	cpu_eb1n : in std_logic; -- lower byte [7:0]

	-- data path to CPU (carries both addresses and data)
	cpu_primary_datapath : inout std_logic_vector(15 downto 0);

	-- address path to CPU (address lines)
	cpu_primary_addresspath : in std_logic_vector(9 downto 0);

	-- **************************
	-- ** SDRAM DIRECT Signals **

	-- data path to SDRAM (carries only data)
	sdram_primary_datapath : inout std_logic_vector(15 downto 0);

	-- address lines to SDRAM
	sdram_addr : out std_logic_vector(11 downto 0);

	-- Bank address lines
	sdram_ba0 : out std_logic;
	sdram_ba1 : out std_logic;

	-- DQMB lines
	sdram_dqmb_0_3 : out std_logic;
	sdram_dqmb_4_7 : out std_logic

	);
end component primary_datapath;


end package sdram_package;