------------------------------------------------------------------------------- -- File: mp3_decode_pkg.vhd -- -- Project: Porta-AMP (MP3 player) -- Created by: Daniel Leder -- Date: 10/30/99 -- -- Purpose: This is a package of all components used in the mp3 decoder -- interface of the Porta-AMP project. -- For descriptions of each please see their respective entity which -- are located in "component_name".vhd files. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package mp3_decode_pkg is component shift8bitreg is generic (regwidth : positive := 8); -- default width (actually needs to be -- 8) port (data : in std_logic_vector(regwidth-1 downto 0); -- data to load clock: in std_logic; -- clock at which to shift out bit reset: in std_logic; -- reset to reset register load : in std_logic; -- used to load the register done: buffer std_logic; -- has register finishced loading msb: out std_logic; -- msb being shifted out empty: out std_logic -- shifting complete? ); end component; -- taken from EE552 Lab#4 - written by Dr. Elliot -- component csadder is -- generic (-- width of adder -- datawidth : positive := 12 -- ); -- port(adden1, adden2, adden3 : -- in std_logic_vector(datawidth-1 downto 0); -- sum_part1, sum_part2 : -- buffer std_logic_vector(datawidth downto 0) -- ); -- end component; -- taken from EE552 Lab#4 - written by Daniel Leder -- component cscounter is -- generic (-- width of counter -- counterwidth : positive := 12 -- ); -- port(clock, reset: in std_logic; -- sum, cout : out std_logic_vector(counterwidth-1 downto 0) -- ); -- end component cscounter; component clock_divide is generic(counterwidth: positive := 5); port(clock: in std_logic; -- input clock reset, enable: in std_logic; -- reset and enable clock divider count_part1: in std_logic_vector(counterwidth-1 downto 0); -- part1 of counter count_part2: in std_logic_vector(counterwidth-1 downto 0); -- part2 of counter divided_clock: out std_logic -- new output clock of new period and -- frequency ); end component; -- to emulate what the mp3 chip will do component mp3_chip_emulator is generic (regwidth: positive :=8); port (clock, reset : in std_logic; -- clock and active low reset databit: in std_logic; -- data bit stream from ALTERA done : buffer std_logic; -- flag from the MP3 chip (want more -- data) data : out std_logic_vector(regwidth-1 downto 0) -- to make sure same -- data going in is -- coming out ); end component; component mp3_decode is generic ( datawidth : positive := 16; -- size of the datapath coming in clock_divider : positive := 5); -- value to divide incoming clock -- by to create new clock of ~1MHz port ( --------------------------------------------------------------------------- -- Master Control connections --------------------------------------------------------------------------- mp3_datain : in std_logic_vector(datawidth-1 downto 0); -- input from MC - data from -- RAM/CD-ROM/lpt streaming mp3_enable : in std_logic; -- input from MC - mp3_datain is valid mp3_ready : out std_logic; -- output to MC - request data from RAM -- to pass to decoder chip --------------------------------------------------------------------------- -- ALTERA system signals --------------------------------------------------------------------------- mp3_clock : in std_logic; -- input of system clock mp3_reset : in std_logic; -- reset decoder chip -- and state of mp3decode --------------------------------------------------------------------------- -- External connections to the MP3 decoder chip --------------------------------------------------------------------------- mp3_demand : in std_logic; -- input from MP3 chip - mp3_decoder -- requires data (1) mp3_chipclk : out std_logic; -- output to MP3 chip - new clock ~1MHz mp3_chipresetn: out std_logic; -- output to MP3 chip - reset the MP3 -- decoder chip mp3_dataout : out std_logic -- output to MP3 chip - output a single -- bit which is valid on falling -- edge of mp3_chipclk ); end component; component clk_divide_ff is generic (N : positive := 1); -- divide by 2^N port (clock, enable, reset : in std_logic; clock_out : out std_logic ); end component; component clk_ff is port (clock, reset, enable : in std_logic; clk_out : out std_logic ); end component; component mp3 is generic ( datawidth : positive := 16; -- size of the datapath coming in clock_divider : positive := 5); -- value to divide incoming clock -- by to create new clock of ~1MHz port ( --------------------------------------------------------------------------- -- Master Control connections --------------------------------------------------------------------------- mp3_datain : in std_logic_vector(datawidth-1 downto 0); -- input from MC - data from -- RAM/CD-ROM/lpt streaming mp3_enable : in std_logic; -- input from MC - mp3_datain is valid mp3_ready : out std_logic; -- output to MC - request data from RAM -- to pass to decoder chip --------------------------------------------------------------------------- -- ALTERA system signals --------------------------------------------------------------------------- mp3_clock : in std_logic; -- input of system clock mp3_reset : in std_logic; -- reset decoder chip -- and state of mp3decode --------------------------------------------------------------------------- -- External connections to the MP3 decoder chip --------------------------------------------------------------------------- mp3_demand : in std_logic; -- input from MP3 chip - mp3_decoder -- requires data (1) mp3_chipclk : out std_logic; -- output to MP3 chip - new clock ~1MHz mp3_chipresetn: out std_logic; -- output to MP3 chip - reset the MP3 -- decoder chip mp3_dataout : out std_logic -- output to MP3 chip - output a single -- bit which is valid on falling -- edge of mp3_chipclk ); end component; end mp3_decode_pkg;