-- CMPE498 Interfacing SDRAM to a microprocessor
-- file: ff_behave.vhd
-- Author: Kevin Mlazgar

-- Revision 1.1 99/09/16
-- changed name to ff_behave

-- Revision 1.0  1999/08/28
-- initial revision.
--
-- 

-- This entity basically emulates the actions of a single set/clear
--  FF...
-- Done this way due to a weird error when using more than one
-- lpm_dff in a single entity...
-- The synthesis of this entity is very efficient.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 


entity ff_behave is
    port (
		-- clock
		ff_behave_clk : in std_logic;
		-- reset
		ff_behave_reset : in std_logic;

		-- clear the latched value (somewhat redundant w/ the reset)
		ff_behave_clr : in std_logic;

		-- Active high line which must last at least one rising edge
		-- of the clock cycle...
		ff_behave_set : in std_logic;

		-- latched output
		ff_behave_q : out std_logic
	);
end entity ff_behave;


-- purpose: latches the dff_behave_set until acknowledged
architecture behavior of ff_behave is
    
    type states is (start, set);  -- state enumeration
    signal state : states;  	-- the current state

begin  -- behavior

with state select
    ff_behave_q <= 
    '1' when set,
	'0' when others;

    -- purpose: state machine controlling logic
    -- type:    memoryless
    -- inputs:  ff_behave_clk, ff_behave_set, ff_behave_clr,
	--				ff_behave_reset
    -- outputs: state
    state_logic : process (ff_behave_clk)
    begin  -- process state_logic
	
	if rising_edge(ff_behave_clk) then
		if ff_behave_reset = '1' then
	    	state <= start;
		else
		    case state is

			when start =>
				if ff_behave_set = '1' then
				state <= set;
				else
				state <= start;
				end if;

			when set =>
			    if ff_behave_clr = '1' then
				state <= start;
		    	else
				state <= set;
			    end if;

	    	end case;
		end if;
	end if;
	
    end process state_logic;

end behavior;