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-- Carry-Save Adder
-- Provided in EE552 Lab#4

-- Uses carry-save arithmetic to implement a high speed adder whose
--  output consists of two vectors which can be added together to
--  obtain the unified (actual) sum.

library ieee;
use ieee.std_logic_1164.all;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; 
use ieee.std_logic_unsigned.all; 
library work;
use work.sdram_package.all;

entity csadder is
	generic (
	-- width of adder
	datawidth : positive := 12
	);
	port(adden1, adden2, adden3 : 
			in std_logic_vector(datawidth-1 downto 0);
		sum_part1, sum_part2 : 
			buffer std_logic_vector(datawidth downto 0)
--		sum_unified : 
--			buffer std_logic_vector(datawidth downto 0)
	);
end csadder;
-- sum_part1   full adder sum outputs
-- sum_part2   full adder carry outputs (shifted by one bit)
-- sum_unified sum with all carries propagated (not part of carry-save adder
-- sum_unified = (sum_part1+sum_part2) = (adden1+adden2+adden3)

architecture carry_save_adder of csadder is
begin

sum_part1 <= '0' & (adden1 xor adden2 xor adden3);
sum_part2 <= ((adden1 and adden2) or
                          (adden1 and adden3) or
                          (adden2 and adden3)) & '0';
                          
-- sum_unified is slower, but is only for demonstration purposes
--sum_unified <= sum_part1 + sum_part2;

end carry_save_adder;