EE 552

Final Report
for
Radio Frequency PSK
Transmitter/Receiver


Norman Bo 343026
Kelvin Leung 344621
David Ritter 346468

Abstract

The goal of this project was to implement a digital RF transmitter and receiver. Binary data is transmitted using PSK (Phase Shift Keying) modulation, currently at a carrier frequency of 800 kHz. A receiver, with knowledge of the frequency but not the phase of the carrier, can receive this signal and demodulate it to recover the original signal. Optional enhancements to the project that are not at this time fully tested include a microprocessor interface to both the transmitter and receiver, variable carrier frequencies and data rates, and carrier frequency recovery at the receiver.

NKD1000TX Radio Frequency PSK Transmitter

General Description

The NKD1000TX transmitter is a flexible general purpose PSK modulator/transmitter. The device supports multiple modes of operation, and multiple carrier frequencies and bit transmission rates. The device can be integrated with a microprocessor or other external device through a standard interface. The device also includes a matrix keypad interface for testing purposes.

Features

Keypad test mode
8-bit microprocessor interface
Serial or parallel data input
Carrier frequency: 24.6 kHz to 3.15 MHz
Bit Rate: 96 bps to 1.57 Mbps
No external circuitry required

Electrical Characteristics

Please refer to Altera Flex10K20 documentation.

Application Hints

This section describes details of the operation of the transmitter that may be of use to developers using the device.

The mode signal, selecting keypad test mode or microprocessor control mode, should be asserted at the rising edge of the reset signal.

Keypad test mode operates at a constant carrier frequency of 800 kHz, and a bit rate of 50 kbps. Key presses are decoded into an 8 bit data word based on the row and column of the key pressed.

In microprocessor mode, the RS inputs select one of 4 registers: data register (RS=00), carrier control register (01), hold control register (10), and mode control register (11). The data register is used to supply 8 bit data words for transmission. The carrier control and hold registers should be written to with a logic 1 in one of the bit positions. The position specifies the clock divider used, according to the following table:

 

Bit position (N) Divider (D)
1 2
2 4
3 8
4 16
5 32
6 64
7 128
8 256

The carrier frequency is determined by dividing the external oscillator frequency by 4 * DCarrier. The bit rate is equal to the carrier frequency divided by DHold.

The mode control register is as shown:

7 6 5 4 3 2 1 0
X X X X X X X SM

The SM bit selects serial input mode. In this mode, the data stream modulated by the carrier is taken from an input pin to the device. A clock at the appropriate rate of bit transmission is supplied as an output.

The tx_signal output pin can be connected directly to an antenna. The signal can be buffered and amplified before transmission, if desired.

Implementation Details

The device is implemented on an Altera Flex10K20 FPGA. The device requires 315 logic cells. It can operate with an external oscillator frequency of up to 28.01 MHz.

Pinouts

 

Signal FPGA Pin Altera Board Pin
o_row0 109 FlexB 15
o_row1 111 FlexB 17
o_row2 114 FlexB 19
o_row3 116 FlexB 21
i_col0 118 FlexB 23
i_col1 120 FlexB 25
i_col2 127 FlexB 27
i_col3 129 FlexB 29
i_mode 50 FlexA 19
o_tx_signal 53 FlexA 21
i_osc 91 Clock
i_reset 28 PB A
i_en 175 FlexC 15
i_cs 181 FlexC 16
i_rs0 182 FlexC 17
i_rs1 183 FlexC 18
i_dataword0 184 FlexC 19
i_dataword1 185 FlexC 20
i_dataword2 186 FlexC 21
i_dataword3 187 FlexC 22
i_dataword4 188 FlexC 23
i_dataword5 190 FlexC 24
i_dataword6 191 FlexC 25
i_dataword7 192 FlexC 26

NKD1000RX Radio Frequency PSK Receiver 

General Description

The NKD1000RX receiver is a flexible general purpose PSK demodulator/receiver. The device provides two demodulation modes, and can receive signals at multiple carrier frequencies and bit transmission rates. The device can be integrated with a microprocessor or other external device through a standard interface. The device also includes 7 segment LED output for testing purposes.

Features 

Electrical Characteristics

Please refer to Altera Flex10K20 documentation.

Application Hints

This section describes details of the operation of the receiver that may be of use to developers using the device.

The mode signal, selecting either test mode or clock recovery mode, should be asserted at the rising edge of the reset signal.

Test mode supports a signal carrier frequency of 800 kHz and a bit rate of 50 kbps only.

Clock recovery mode allows recovery of signals with carrier frequencies up to 3.15 MHz and as low as 24.6 kHz.

Implementation Details

The device is implemented on an Altera Flex10K20 FPGA. The device requires 366 logic cells. It can operate with an external oscillator frequency of up to 26.88 MHz.

 

Pinouts

 

Signal FPGA Pin Altera Board Pin
i_clock 91 Clock
i_reset 28 PB A
i_mode 70 FlexA 33
i_rx_signal 53 FlexA 21
o_led0 17 Digit2a
o_led1 18 Digit2b
o_led2 19 Digit2c
o_led3 20 Digit2d
o_led4 21 Digit2e
o_led5 23 Digit2f
o_led6 24 Digit2g
o_led7 25 Digit2dec
o_valid 109 FlexB 15
o_word0 111 FlexB 17
o_word1 114 FlexB 19
o_word2 116 FlexB 21
o_word3 118 FlexB 23
o_word4 120 FlexB 25
o_word5 127 FlexB 27
o_word6 129 FlexB 29
o_word7 132 FlexB 31

  

1.0 Project Overview *

1.1 Digital transmitter *

1.1.1 Keypad Decoder *

1.1.2 Buffer *

1.1.3 Parallel to Serial Converter *

1.1.4 Mixer *

1.1.5 Clock Generator *

1.1.6 Transmitter *

1.2 Digital Receiver *

1.2.1 Serial to Parallel Converter *

1.2.2 Demodulator *

1.2.3 Sample Pulse Generator *

1.2.4 Liquid Crystal Display Driver *

1.3 Additional Features (Untested) *

1.3.1 Microprocessor Interface *

1.3.2 Clock Recovery *

2.0 Design Details *

2.1 Transmitter *

2.1.1 Keypad Interface *

2.1.2 Microprocessor Interface *

2.1.3 Buffer *

2.1.4 Parallel to Serial Converter *

2.1.5 Carrier/Clock Generator *

2.1.6 Mixer *

2.2 Receiver *

2.2.1 Pulse Generator *

2.2.2 Demodulator *

2.2.3 Clock Recovery *

2.2.4 Serial to Parallel Converter *

2.3 External Circuitry *

2.4 IF Theory *

3.0 Experiments *

3.1 Design Experiments *

3.1.1 Transmitter *

3.1.2 Receiver *

3.2 Logic Cell Requirement Experiments *

3.3 Clock Speed Experiments *

4.0 Design Verification *

4.1 Receiver Entities *

4.2 Transmitter Entities *

5.0 IC Test Measurements *

6.0 Design Documentation *

6.1 e_transmitter *

6.2 e_clock_gen *

6.3 e_keypad *

6.4 e_control *

6.5 e_buffer *

6.6 e_ps *

6.7 e_mixer *

6.8 e_rxer *

6.9 e_demod *

6.10 e_pulse_gen *

6.11 e_clock_recover *

6.12 e_sp *

7.0 References *

1.0 Project Overview

A digitally synthesized radio transmitter and receiver are to be constructed to send and receive digital data.

Input data from a matrix keypad is buffered, and converted from parallel to serial form. These serial data are used to modulate the carrier. The modulated signal is then sent to a buffer and transmitted to the antenna. The transmitter is designed to have a carrier frequency of approximately 800kHz.

A microprocessor interface is available at the transmitter for data and control information. With the microprocessor interface, the transmitter is capable of providing multiple carrier frequencies and bit transmission rates.

The modulated signal is received by the antenna at the receiver. The signal is then amplified and sent to a fast comparator to adjust the signal level. The digital signal is then demodulated and de-framed. The final 8-bit word of data is then recovered.

1.1 Digital transmitter

 

1.1.1 Keypad Decoder

The keypad decoder polls the keypad by writing a single 0 bit to one of the lines of the keypad. The column lines are checked for 0 bits. Any 0 bits found indicate a key is pressed. The bit vector corresponding to the key press is formed by concatenating the row lines that were output with the received column lines.

1.1.2 Buffer

The buffer stores the decoded data from the keypad and latches to the parallel to serial converter when data request is enabled from the converter. The buffer also sends a data valid signal to the converter. When the buffer is empty, the valid signal will fall. It is in the buffer stage that the 8-bit word is combined with the framing bits (1102).

1.1.3 Parallel to Serial Converter

The converter accepts an 11-bit frame from the buffer and outputs a serial stream of data bits. The most significant bit of the input frame is the first bit output by the converter. The converter generates a data valid signal to the mixer to indicate that the data should be transmitted.

1.1.4 Mixer

The mixer modulates the serial stream of data bits from the P/S converter with the carrier square waves generated in the clock generator entity. The mixer is enabled by the data valid signal from the P/S converter; if the valid signal is low, no transmission will occur.

1.1.5 Clock Generator

The clock generator is used to generate a clock with lower frequency. It accepts the 25.175MHz signal from the crystal on the Altera board. Using counters, this entity generates the two carrier square waves, along with a system clock.

1.1.6 Transmitter

The transmitter entity combines the components of the transmitter. This entity includes logic to select appropriate inputs for each entity. The selection is controlled by the Mode input, and by the microprocessor interface entity, e_control. Input to the buffer can be taken from the keypad or from the microprocessor interface. Input to the mixer can be taken from the p/s converter or from an external serial data source.

1.2 Digital Receiver

1.2.1 Serial to Parallel Converter

The converter accepts a series of bits from the demodulator and outputs a parallel stream of data. Eleven bits of data are received and stored in a buffer for de-framing. The framing bits 1102 are compared to the first three bits of the data. If they are identical, the low order 8 bits of data are output, and the valid signal is asserted. If they are different, the data will be shifted by one bit with each new serial bit. The first three bits are again compared to the framing bits until they match. The converter generates an output valid signal (o_valid) to indicate that the data is correct.

1.2.2 Demodulator

The demodulator is implemented as a finite state machine. When it detects a bit stream of 11002 (indicating a 1 before modulation), it will output (serially) 11112, when it sees 01102 (indicating a 0 before modulation), it will output 00002. When the demodulator finishes demodulating the 8-bit signal, it will return to the ‘stop’ state and generates a stop signal. Note that the pulse generator will generate a clock at the rate of bit reception, which will indicate when the s/p converter should sample the demodulator output.

1.2.3 Sample Pulse Generator

The generator is initiated by the rising edge of the received signal from the antenna. If there is no signal being transmitted, the pulse generator will stop all other receiver components. The pulse generator will generate sampling pulses at 1/8, 3/8, 5/8 and 7/8 of a carrier period, and will also generate a bit clock which will be used to clock the s/p converter.

1.2.4 Liquid Crystal Display Driver

This entity is used to initialise and write received data from the receiver onto the LCD screen. The entity is completed but not yet implemented onto the receiver. Ultimately, it will replace the LED we have right now that displays the received signal. This entity is a combination of different VHDL LCD driver that different groups have used in the pass, with some modification added to fit our needs. What it will do is that it will initialise the LCD when the reset button is pushed and it will decode and write the received signal onto the LCD when both a valid signal and a 8-bit vector is received.

1.3 Additional Features (Untested)

1.3.1 Microprocessor Interface

This component provides a microprocessor interface with the transmitter. The operation of the interface is fully described in the test cases. Note that while the e_control entity that implements this entity has been fully tested, the operation of this entity within the transmitter has not been verified.

1.3.2 Clock Recovery

The clock recovery component provides an alternate method of recovering the data signal from a modulated signal. The clock recovery entity requires no knowledge of the carrier frequency or the rate of bit transmission, although the oscillator frequency should be the same as that used by the transmitter. The carrier frequency can be at most 1/8 of the oscillator frequency.

The clock recovery method first determines the length of a received pulse, and uses this as a reference to determine when to sample later pulses. The number of equal width pulses is then used to determine the bit rate. Since the frame bits "110" initiate each frame, the number of carrier cycles per bit is one half the number of equal width pulses.

With the carrier and bit rates determined, the sampling and decoding method is similar to that used in the demodulator component described above.

2.0 Design Details

Note that simulation of each entity has been performed and the results are included in appendix B. These simulations can be used as supplemental information regarding the operation of each component described in the following section.

2.1 Transmitter

The transmitter is composed of 6 functional blocks. These blocks are the clock/carrier generator, mixer, parallel to serial converter, input buffer, keypad interface and microprocessor interface.

The design is based on the use of a multiplexer as a mixer. The data bit to be transmitted is used to select one of two separate carriers, which are separated in phase by 90 degrees. The two carriers are generated by the clock generator module. The data bits are supplied by the parallel to serial converter, which in turn is supplied with data through the input buffer, which receives input from either the keypad interface or the microprocessor interface.

The function of each block is described below.

2.1.1 Keypad Interface

The keypad interface is primarily included in the design for purposes of testing. Using a keypad provides a simple method to provide data to the transmitter.

The keypad interface operates by polling the keypad continuously. On alternate clock cycles, the row lines are and the columns are read and tested. Each row is individually driven low, and columns are tested for '0' bits. Each '0' column indicates a key is pressed. The key press is assigned an 8-bit code based on the row and column values. The 8-bit code is inefficient for storing a 4x4 matrix keypad key press. However, it is capable of storing multiple simultaneous key presses. Also, as the purpose of the keypad is as a testing mechanism, it provides a simple testing mechanism for the transmitter.

Note that key debouncing is accomplished by using a slow clock for polling the keypad, combined with the process of writing rows and reading columns on alternate clock cycles.

The keypad interface communicates with the rest of the transmitter through an 8-bit parallel data word, and a control signal, new, which is pulsed when a new key press is detected.

2.1.2 Microprocessor Interface

The microprocessor interface provides data and control registers which can be written to by external devices. This interface is only enabled in microprocessor control mode.

The EN signal must be low. This input can be connected to a microprocessor's read/write output. The CS signal is the device chip select. The RS signals are the transmitter's register select inputs. These can be connected to a microprocessor's address lines.

Data from the 8-bit data bus is read on the rising edge of CS. The value of the RS lines is used to determine the destination of the data.

For RS=00, the data is written to the data register. This causes the microprocessor interface to pulse the new signal, and to supply the 8-bit word to the buffer.

For RS=01, the carrier control register is written to. The data is decoded using the following scheme. From the lowest bit to the highest, each bit is tested. The highest bit which is set is used to determine the clock divider used to generate the carriers. If bit 0 is set, the divider is set to 2. If bit 1 is set, the divider is set to 4. In other words, if bit n is set, the divider is set to 2n+1. Since the carrier is pre-divided by 4, this allows dividers from 8 to 1024 to be applied when generating the carrier, and allows carrier frequencies from 3.15 MHz down to 24.6 kHz to be specified.

For RS=10, the hold control register is written to. The data is decoded using the same method applied to the carrier control register. This divider determines the number of carrier periods for which each data bit is held. Each bit can be held for 2 to 256 carrier periods. Thus, the data rate depends on both the carrier frequency and the bit hold duration, and can vary from 96 bps to 1.57 Mbps.

RS=11 selects the mode control register. The most significant 7 bits are ignored. The least significant bit selects serial input mode. In this mode, data is taken from an external serial data source instead of from the parallel to serial converter.

2.1.3 Buffer

The buffer stores input data words until the parallel to serial converter is ready to accept them. This buffer only has a capacity of one word. When using keypad test mode, this is acceptable, as the key debouncing cycle ensures that data words arrive at well separated intervals. When using the microprocessor interface, the external device should only write data words if the request line is high, indicating that the parallel to serial converter is ready to accept data.

The buffer detects pulses on the new signal to determine when to read data words from the microprocessor interface or the keypad. If the buffer currently contains valid data, this new data will be discarded. Otherwise, the data will be read, and the word_valid signal will be asserted. If the request signal falls while word_valid is asserted, the output of the buffer has been latched by the parallel to serial converter, and the buffer can now accept new data. The word_valid signal will be driven low to indicate that the data in the buffer has already been used.

The buffer is also responsible for adding frame bits to each data word. The 3 bit Barker code 1102 is added to the beginning of each word, and a stop bit, 1, is added to the end of each word.

2.1.4 Parallel to Serial Converter

This converter takes as input a 12-bit frame from the buffer component. The frame is read from the buffer if the converter has asserted request and the word_valid signal is high. When the frame has been read, the request line will be driven low. When a new frame is read into the parallel to serial converter, the converter begins outputting serial bits from the MSB to the LSB. While the frame is being converted, the converter asserts the bit_valid signal. This indicates to the mixer that a data word is being transmitted. When the frame is completely converted, the bit_valid signal will be driven low.

The rate at which bits are output from the converter is determined by the bit rate clock, whose frequency depends on the mode of operation and the values of the carrier and hold control registers described in the previous section.

2.1.5 Carrier/Clock Generator

This component is responsible for generating clocks and carriers for the other components of the transmitter.

A master clock is generated by dividing the external oscillator frequency by 2. This master clock is used to generate the carriers and other clocks. To generate the carriers, and a counter is used to count up to the required carrier divider. This divider is either preset when in test mode, or set by the microprocessor interface when in microprocessor mode. When the count reaches the required value, a flag is used to determine which carrier should be changed. Based on this flag, a transition is forced on one of the carriers. This operation causes the two carriers to be separated in phase by 90 degrees.

Another counter is used to count the transitions of carrier1. When this counter reaches the value specified for the bit clock rate (either by the microprocessor interface or preset when in test mode), a transition on the bit rate clock will be forced.

Carriers are generated according to the following diagram, where the common clock is the master system clock, o_clock.

2.1.6 Mixer

The two carriers generated by the clock generator are supplied as inputs to a multiplexer. The select input of the multiplexer is created by synchronising the output of the parallel to serial converter with the rising edge of carrier1. This synchronisation forces data transitions to occur at predictable positions in the transmitter waveform, and thus simplifies the decoding process.

The output of this multiplexer is supplied to another multiplexer as one input. The other input is tied to ground. The select input is the bit_valid signal. This causes the transmitter to turn off when no valid data is being transmitted.

The operation of the mixer can be summarised by the following diagrams, which show the mixer’s operation when the enable input is high. When the enable input is low, the output of the mixer will be low.

The above diagram shows the waveform resulting from a 0 to 1 transition.

2.2 Receiver

The receiver uses two methods to decode received signals. The first method uses a finite state machine, which sample the received waveform at specific points to detect transitions in the data. To ensure that the waveform is sampled at the correct points, a sampling pulse generator is used, which bases sampling pulse position on the timing of the initiating start bit and the known carrier frequency. The second method, clock recovery, does not require a known carrier frequency. Its operation is described in detail below.

2.2.1 Pulse Generator

This module is responsible for generating sampling pulses as well as the bit rate clock for test mode operation of the receiver. The clocks are generated only when the receiver is not stopped. When stopped, the pulse generator does not generate clocks. When a rising edge on the received signal is detected, the generation of pulses starts. This is accomplished using clock dividers. Pulses are generated at 1/8, 3/8, 5/8 and 7/8 of a carrier period. These pulses are used to clock the demodulator FSM. The bit rate clock is generated with a falling edge at the midpoint of each data bit. To provide this edge, a counter is used to count sampling pulses.

When the demodulator FSM determines that the signal has stopped, it will assert the stop signal. When this signal is asserted, the pulse generator will stop generating sampling and bit rate clocks, until a new rising edge on the received signal is detected.

The operation of the pulse generator is summarised by the following diagram:

In addition, a bit rate clock is generated based on the bit rate clock divider, which is hard coded into the pulse generator. The number of sampling pulses is counted to determine when transitions should occur on the bit rate clock.

2.2.2 Demodulator

Demodulation is accomplished using a FSM. The state diagram is included on the following page. The clock for the FSM is provided by the pulse generator component. The input is read from the received signal. The outputs are the decoded signal and the stop signal, respectively.

2.2.3 Clock Recovery

This component is intended to allow recovery of signals without knowledge of the carrier rate of the bit rate. Recovery is based on the start bits, 110. By counting the width of each of the first two pulses, the receiver can determine the carrier frequency. By counting the number of equal width pulses, the bit rate can be determined. The first unequal width pulse will occur at the 1 to 0 transition at the beginning of the third start bit. Thus, the number of equal width pulses can be divided by 2 to determine the number of pulses in each bit.

After determining the carrier frequency and the bit width, this component will continue to measure pulse width to detect transitions in the data bits.

Note that this component replaces both the pulse generator and demodulator FSM when operating in clock recovery mode.

The series of steps used in decoding a received waveform is described below. The execution of these steps is controlled by a FSM.

 

Determine width of first 1 pulse by counting at fast clock rate.
Determine width of first 0 pulse.
Count the number of equal width pulses.
Determine the width and logic level of the transition pulse. This pulse indicates a 1 to 0 transition.
Decode the remaining bits. During this process the following steps are performed
Force transitions on the bit rate clock twice per bit. Output the data bit at the rising edge, ensuring that it will be ready when read at the falling edge of the clock.
Measure the width of each pulse. Noting that transitions occur on either logic level 1 pulses or logic level 0 pulses (not both), one type of pulse can be ignored. If the pulse width is different than the normal pulse width, as determined in step 1 or 2, a transition is known to have occurred. The 1 to 0 transition width has been determined in step 4, and it is used to determine if the transition is a 1 to 0 transition or a 0 to 1 transition. The appropriate output bit is placed in an output buffer.
Output remaining bits in buffer. 

2.2.4 Serial to Parallel Converter 

This converter receives data bits from either the demodulator FSM or the clock recovery component. The bits are read on the falling edge of the bit rate clock, which is generated by either the pulse generator or the clock recovery module. The bits are placed in a 12- bit buffer in the order in which they are received. When the buffer is full, the most significant 3 bits are compared to the expected frame bits, 110. If a match is detected, the 8 data bits are latched to the output and the valid signal is pulsed. This pulse can be used as an interrupt for an external microprocessor, which can then read from the parallel output. Note that tri-state buffers should be placed between the parallel output and the microprocessor.

 If the frame bits do not match, the data in the buffer will be shifted by one bit as each new bit is received, until a match is detected.

The output is also decoded into 7-segment display outputs for testing purposes.

 The operation of the serial to parallel converter is summarised by the following diagram:

3.0 Experiments

3.1 Design Experiments

These are experiments that were performed to improve the design or implementation of specific components of the project. These changes were made not to improve space or speed considerations.

3.1.1 Transmitter

Aside from miscellaneous coding errors, few changes were made to the original design of the transmitter. The one relatively major change made to the transmitter was the addition of a stop bit to the transmitted frame. This change was necessitated by the design of the receiver, and does not reflect any requirements of the transmitter itself.

3.1.2 Receiver

The receiver's initial design was extended with the clock recovery module. This module was written twice. The first attempted clock recovery method used the width of the initial pulses to determine when to sample the waveform. The second method measures the width of every pulse, and uses variations in pulse width to determine the data bits being received.

The first method works reasonably well under controlled conditions. The fact that it uses pulse widths to determine sampling intervals means that a divider must be used. This divider can be implemented by shifting, since sampling intervals occur at multiples of 1/4 of a pulse width (1/8 of a carrier period). However, when the pulse width is small and not a multiple of 4, the division is only an approximation. The error in dividing results in improper spacing of sampling intervals, and will result in erroneous decoding of the received waveform. Thus, the original clock recovery scheme will only work if the pulses are large, compared to the fast receiver clock, or if the pulse width is a multiple of 4 times the fast receiver clock.

The second method corrects this problem by largely eliminating the need for division. Division in this scheme is used only to determine the location of the output bit clock transitions, and not in decoding the received waveform.

3.2 Logic Cell Requirement Experiments

Experiments regarding chip area used were largely unnecessary in this project. Both devices will easily fit on a single Flex10K20 FPGA. As they are designed to be separate devices, they are not normally placed on a single FPGA. When separate, the devices fit even more easily on the FPGA's. The only modifications made to the code to reduce chip area used was to specify ranges on integer type variables.

3.3 Clock Speed Experiments

Device speed also proved to be acceptable in most cases. The transmitter can operate with a clock speed of up to 28 MHz. The receiver can also operate at speeds greater than that of the supplied external oscillator, with the exception of the clock recovery module. This module can operate at approximately half the rate of the supplied oscillator. The clock is divided before supplying it to this module.

The effect of the slower rate of operation of the clock recovery module is that it cannot demodulate signals with a carrier frequency of greater than 3.15 MHz. As this is the current maximum carrier frequency of the transmitter, this limitation is acceptable.

4.0 Design Verification

Simulation results are included in appendix B.

4.1 Receiver Entities

Entity Case Purpose Description
Pulse Generator

1

 Verify sampling pulse generation. This test case demonstrates the normal operation of the Pulse Generator. The output waveform of this test case is attached in the appendix, labeled "Operation of Pulse Generator I." For this test case, a clock (i_osc) signal of 20MHz is fed into the device. When reset (i_reset) is ‘0’, the device does not do anything. When an input (i_rx_signal) of ‘1’ is received for the first time, the pulse generator is turned on. The pulse signal, o_pulse, which is ½ the frequency of the input clock frequency, is generated. Another output signal, o_bitclock, which is1/8 the frequency of the input clock frequency, is also generated. This operation is verified by the attached waveforms.
 

2

 Verify start/stop of pulse generation. This test case demonstrates the operation of the Pulse Generator when a number of pulses is received and the when a stop signal is received. The output waveform of this test case is attached in the appendix, labeled "Operation of the Pulse Generator II." For this test case, the same clock in case #1 is used. When a rising edge on i_rx_signal is received, the pulse generator is turned on and the two output clocks starts to run. Further edges on i_rx_signal do not affect this operation. When a rising edge on i_stop is detected, the pulse generator is turned off and no signal is generated on the two output clocks. This operation is verified by the attached waveforms.
Demodulator

1

 Verify correct decoding by FSM. In this test case, the normal operation of the demodulator is demonstrated. The output waveform of this test case is attached in the appendix, labeled "Operation of Demodulator I." For this test case, a clock (i_clock) signal of 20MHz is fed into this device. When reset (i_reset) is ‘0’, the FSM stays at the stop state and outputs (o_output) ‘01’. While the FSM input is 0, the demodulator will remain in the stop state. When a 1 is received, the FSM will begin decoding pulses. While sequences of ‘1100’ is received, the FSM will output ‘10’. When a ‘11000’ sequence is received, the FSM will begin outputting ‘00’, and will continue to do so while additional ‘1100’ sequences are detected. When a ‘1101’ sequence is received, the FSM should again output ‘10’ while ‘1100’ sequences are received. This operation is verified by the attached waveform.
 

2

 Verify stop state operation This test case demonstrates the operation of the demodulator when long sequences of ‘0’ are received. The output waveform of this test case is attached in the appendix, labeled "Operation of Demodulator II." The same clock in test case #1 is used here. The FSM is turned on by the input sequence ‘1100’ but stop at the stop state when a long string of ‘0’s’ is received. The FSM is turned on again when the input sequence of ‘1100’ is received. This operation is verified by the attached waveform.
 

3

 Verify operation under glitches This test case demonstrates the operation of the demodulator when glitches of data is received. The output waveform is attached in the appendix, labeled "Operation of Demodulator III". The device first receives an input sequence of ‘1100’, which turns on the FSM. After that, a single bit of ‘1’ is received. The FSM should jump to the stop state as a single pulse of logic ‘1’ is unexpected and invalid in the received waveform. Another glitch is received after starting the FSM and receiving the valid inputs ‘11000110’. The FSM is again expected to stop operation on receiving this glitch. This operation is verified by the attached waveform.
Serial to Parallel Converter

1

 Verify reception of correct frame The serial to parallel converter is tested to verify correct reception of frames with valid frame bits. To test this operation, a series of bits ‘11001100000’ is used as input to the serial to parallel converter entity. After receiving all 11 bits of input, the s/p converter is to output the frame with the frame bits stripped on the o_word signal, and assert the o_valid signal to indicate a new valid word of data has been received. The s/p converter is then to begin receiving a new 11 bit frame. The attached waveform labeled "Operation of S/P Converter verifies this operation. Test case 1 is located on page 1 of this simulation.
 

2

 Verify reception of invalid frames The serial to parallel converter is tested to verify proper reception of invalid frames. When the series of bits received does not contain the valid frame bits, the receiver does not assert the valid signal after receiving all 11 bits. This operation is verified by the attached waveform, "Operation of S/P Converter". Test case 2 is located on page 2 of this simulation.
 

3

 Verify frame resynchronization. The serial to parallel converter is tested to verify frame resynchronization. After receiving an invalid frame, the s/p converter will the received bits as new bits are received, until correct frame bits are detected. When the frame bits are detected, the o_valid signal will be asserted, and the stripped frame will be output on the o_word signal. This operation is verified by the attached waveform, "Operation of S/P Converter". Test case 3 is located on page 2 of the simulation.
Clock Recovery

1

 Verify carrier and bit rate recovery. The clock recovery entity is tested to verify that the carrier rate and bit rate can be recovered, and that the modulated waveform can be properly decoded. A modulated signal representing the bit sequency "11001" is supplied. The pulse width is 8 oscillator cycles, and the bit rate is 1 bit per carrier period. The output bitstream should consist of the sequency "11001" at the falling edges of the bit clock. This operation is verified by the attached waveform, "Operation of Clock Recovery".
Receiver

1

 Verify overall receiver operation An example of receiver operation is included, with all control signals displayed. A stream of 11 bit data (representing the transmitted signal) is received and latch to the serial to parallel converter. The converter removed the framing bit (the first 3 bits) and latch the remaining 8 bits of data to the demodulator. The signal s_output contains the output from the demodulator. The o_valid signal is triggered when the demodulating process is complete. The resulting signal is stored in the o_word.

 

4.2 Transmitter Entities

Entity Case Purpose Description
Clock Generator 1 Verify correct generation of clock and carrier signals. The clock generator circuit is tested to verify correct generation of clocks and carrier signals. With i_div = 0, the o_clock signal should have a transition on each rising edge of the external oscillator. The o_carrier0 and o_carrier1 alternately have transitions on the rising edge of o_clock. O_clock_bit is a duplicate of o_carrier1. This operation is verified by the attached waveform, "Operation of Clock Generator I".
  2 Verify variable clock frequency control. The clock generator is tested to verify that variable clock and carrier frequencies can be generated. To test this, i_div is set to 2. Three external oscillator periods are required for each transition on o_clock. The relationship between o_clock on the other clock and carrier signals remains the same as in case 1. This operation is verified by the attached waveform, "Operation of Clock Generator II".
  3 Verify ASK carrier generation. With the i_type input set to ‘0’, the clock generator is to generate carrier signals appropriate for generating Amplitude Shift Keying signals. In this case, carrier0 is set to a constant logic ‘0’, while carrier1 retains the form found in cases 1 and 2. This operation is verified by the attached waveform, "Operation of Clock Generator III".
Mixer 1 Verify operation with valid input data. The mixer is tested using appropriate carrier waves i_carrier1 and i_carrier0, separated in phase by 90 degrees. A series of input bits are supplied while the i_valid signal is asserted. The o_tx_signal should consist of a series of pulses with longer or shorter troughs indicating transitions from 1 to 0 and from 0 to 1 respectively. This operation is verified by the attached waveform, "Operation of Mixer I".
  2 Verify operation with invalid data. The mixer is tested using appropriate carrier waves i_carrier0 and i_carrier1, as in case 1. The same series of input bits is supplied, but with the i_valid input low for some of the input bits. While i_valid is low, the transmitter should disregard the input bits and output a constant logic 0. This operation is verified by the attached waveform, "Operation of Mixer II".
Parallel to Serial Converter 1 Verify operation of parallel to serial converter. The p/s converter is supplied with a frame of data, and i_valid is asserted. The p/s converter should de-assert the request line after latching the input frame, and should the begin outputting the data bits starting with the MSB. While the data bits are being output, the o_valid signal should be asserted. After completing the conversion, the o_valid line should be de-asserted, and the request line should be asserted. This operation is verified by the attached waveform, "Operation of P/S Converter I".
  2 Verify variable bit hold time. The p/s converter operation is reexamined using a different hold divider. The operation should be identical, except that the time scale will be different. In this test case, the i_div input is decreased from 3 to 0. The p/s converter should output the series of bits at 4 times the rate of case 1. This operation is verified by the attached waveform, "Operation of P/S Converter II".
Buffer 1 Verify operation when no valid data exists. The buffer is tested without providing any valid input data. The buffer should hold o_valid at logic 0 regardless of the value of i_request. This operation is verified by the attached waveform, "Operation of Buffer I".
  2 Verify operation when new valid data arrives. While i_request is asserted, a new data word is input by placing the word on i_word and asserting i_new. The word should be latched to the output, with the frame bits added, and the o_valid signal should be asserted. This operation is verified by the attached waveform, "Operation of Buffer I".
  3 Verify operation when new valid data arrives. While i_request is not asserted, new data is supplied as described in case 2. The data should not be latched to the output, and the o_valid signal should remain unchanged. This operation is verified by the attached waveform, "Operation of Buffer II".
  4 Verify operation when request asserted while valid data exists After supplying valid data as in case 3, the i_request line is asserted. After i_request is asserted, the data should be latched to the output, and o_valid should be asserted. This operation is verified by the attached waveform, "Operation of Buffer II".
Keypad 1 Verify reception of keypresses. The keypad polling entity is tested by supplying simulated keypresses. Keypresses are simulated by asserting one column line to logic 0 when a row line is polled. Consecutive keypresses are simulated, one corresponding to row0, column1, the other to row0, column3. The o_new signal should be asserted on each keypress, and the row and column signals should be latched to the upper and lower 4 bits of the output data word respectively. This operation is verified by the attached waveform, "Operation of Keypad".
Micro-

Processor interface

 1 Verify correct operation of data register. The microprocessor interface operates using bus control signals i_en, i_cs, i_rs, and an 8 bit data bus i_data. The i_en signal corresponds to R/W. When enabled, the rising edge of i_cs is used to latch data. The i_rs lines select the register. With i_rs = ‘00’, the data register is selected, and the i_data signal should be latched to o_data signal, and the o_new signal should be asserted to indicate a new word has been received. This operation is verified by the attached waveform, "Operation of Microprocessor Interface I".
  2 Verify correct operation of hold control register The hold control register is indicated by i_rs = ‘01’. When the hold control register is selected and a rising edge on chip select occurs, the value of o_holddiv should be set based on the value of i_data. The o_holddiv signal is used to determine the number of carrier periods each data bit will be held for. The correct operation of this test case is verified by the attached waveform, "Operation of Microprocessor Interface II".
  3 Verify correct operation of clock control register The clock control register is indicated by i_rs = ‘10’, and is used to change the clock and carrier frequencies of the transmitter. When the clock control register is selected and a rising edge on chip select occurs, the value of o_clockdiv should by set based on the value of i_data. This operation is verified by the attached waveform, "Operation of Microprocessor Interface III".
  4 Verify correct operation of misc. control register The miscellaneous control register is indicated by i_rs = ‘11’. It allows control of other aspects of the transmitter operation. At this time, only bit 0 has a meaning, and it indicates serial input operation. When high, this bit indicates that input should be taken serially from an input pin on the transmitter. When the miscellaneous control register is selected and a rising edge on chip select occurs, the value of i_data(0) should be latched to the output o_bitmode. This operation is verified by the attached waveform, "Operation of Microprocessor Interface IV".
Transmitter 1 Verify overall transmitter operation An example of transmitter operation is included, with all control signals displayed. The carrier and hold control registers are written to, to modify the carrier frequency and bit rate. A data word is written to the data register, at which point transmission begins. The handshaking signals from the microprocessor interface to the mixer are shown. The data transitions, visible as elongated and shortened pulses in the transmitted waveform, are displayed. The results of the simlation are included in the attached waveform, "Operation of Transmitter".

 5.0 IC Test Measurements

Testing of the complete designed was performed using digital oscilloscope readings to verify correct generation of transmitted waveforms and to verify correct operation of the receiver. The use of these tools was complemented by the use of the keypad and LED test mechanisms.

Internal operations of the devices were analysed using the oscilloscope by exporting internal signals as buffer outputs in each entities port definition. This aided in debugging the circuit.

Final correct operation of the system was verified using the keypad and LED test mechanisms. If the output of the LED matched the key pressed, the system's operation was verified.

6.0 Design Documentation

A description of each design entity follows.

6.1 e_transmitter

This entity incorporates the individual components of the transmitter. This entity also defines the data paths between the entities. In several cases control signals determine the source of data for input to an entity. The mode signal selects the new signal and the word signal from either the e_keypad entity or the e_control entity as input to the e_buffer entity. The bitmode signal from the e_control entity selects the bitstream input for the mixer, from either the e_ps entity or from the external bitstream input.

The components instantiated in this entity are described below: e_clock_gen, e_mixer, e_keypad, e_control, e_buffer, and e_ps.

The port definition for this entity exports many internal signals as buffer outputs. These signals are prefixed by a s_ or v_ indicator. These signals can be ignored externally. The signals prefixed by i_ and o_ are true input or output signals, and are listed below:

i_osc : external oscillator

i_reset : system reset

i_mode : mode select (keypad test = 0, microprocessor control = 1)

i_cols : keypad column lines

o_rows : keypad row lines

o_tx_signal : modulated signal

o_clock_bit : bit rate clock (for external serial data sources)

i_dataword : 8-bit data port (for microprocessor interface)

i_rs : register select

i_cs : chip select

i_en : enable (equivelant to R/W)

i_bitstream1 : external serial data input

 6.2 e_clock_gen

This entity is responsible for generating carriers and system clocks for the transmitter. The operation of the clock generator is described in section 2.1.5.

The port definition for e_clock_gen includes the following signals:

i_osc : external oscillator

i_div : carrier frequency clock divider

i_type : modulation type (1 = ASK, 0 = PSK)

o_clock : master clock

o_clock_bit : pre-division bit rate clock

o_carrier0 : carrier representing data at logic '0'

o_carrier1 : carrier representing data at logic '1'

6.3 e_keypad

The e_keypad entity polls an 4x4 matrix keypad at a reduced clock rate. The master system clock is divided by 218 to determine the rate of keypad polling. The column lines are read on alternate clock cycles to ensure that key presses are debounced.

 

When a key press is detected, an 8-bit word is latched to the word output of the e_keypad component, and the new signal is pulsed.

 

The operation of this component is further described in section 2.1.1.

 

The port definition of the e_keypad entity includes the following signals:

 

i_clock : master system clock

i_reset : system reset

o_word : output data word

o_new : new data signal

o_rows : keypad row lines

i_cols : keypad column lines

6.4 e_control

The e_control entity defines the microprocessor interface to the transmitter.

As described above, data is latched to the appropriate register on the rising edge of the CS input, if the EN is low. The meaning of each register is described in section 2.1.2.

After latching the data to the appropriate register, the data is synchronized with the master system clock before being output to the rest of the transmitter.

The port definition of the e_control entity includes the following signals:

i_en : enable (R/W)

i_rs : register select

i_cs : chip select

i_clk : master system clock

i_reset : system reset

i_data : input parallel data port

o_data : output data word (data to be transmitted)

o_new : new data signal

o_bitmode : serial data input mode select

o_clock_bit : bit rate clock (for external serial data sources)

o_clockdiv : carrier frequency clock divider

o_holddiv : bit rate clock divider

6.5 e_buffer

The input buffer component serves to isolate the parallel to serial converter from the input data sources. This buffer stores a single data word. Once it has received data, it will ignore any incoming data until the stored word has been passed to the p/s converter.

The request line allows the p/s converter to signal the need for data. The new signal allows the data sources (keypad and microprocessor interface) to indicate incoming data.

The e_buffer component also adds the frame bits to the data word.

A complete description of the e_buffer component is included in section 2.1.3

The port definition for the e_buffer component includes the following signals:

i_word : input data word

i_request : output data requested (by p/s converter)

i_new : new data available (from keypad or microprocessor interface)

i_clock : master system clock

i_reset : system reset

o_valid : output data valid (to p/s converter)

o_frame : output data frame (word + frame bits)

 6.6 e_ps

The e_ps component implements a parallel to serial converter. Data frames are latched from the input when the input valid signal is asserted and the request output is high. After latching data, the request line falls until the entire frame has been converted, and the output valid signal is asserted until the frame is converted.

The rate of conversion is determined by the i_div input, which is used to determine the extent of clock division. Each bit is output after i_div clock cycles. The clock used to drive the p/s converter is at the carrier frequency (ie. not the master clock).

The port definition for the e_ps entity includes the following signals:

i_frame : input parallel frame

i_clk : carrier rate clock

i_reset : system reset

o_bitstream : serial output

o_request : new data requested (to buffer)

i_valid : input parallel data valid

i_div : bit rate clock divider

o_valid : serial output valid

6.7 e_mixer

The mixer selects the appropriate carrier signal based on the data input. The enable input is used to stop operation of the mixer. When enable is low, the transmitter output will be a constant logic 0. When high, the appropriate carrier will be transmitted.

A complete description of the mixer is included in section 2.1.6.

The port definition for the e_mixer entity includes the following signals:

i_carrier0 : carrier representing logic 0

i_carrier1 : carrier representing logic 1

i_bitstream : serial input data (to be transmitted)

i_enable : enable (valid output from p/s converter)

i_clock : external oscillator

i_reset : system reset

o_tx_signal : modulated signal

 

6.8 e_rxer

This entity instantiates the individual receiver components. The data paths between the components are also defined in this entity. In particular, the mode input is used to select either the clock recovery module or the FSM demodulator as the source for input to the serial to parallel converter.

The e_rxer component also performs decoding for the seven segment LED output.

The port definition for the e_rxer entity includes the following signals:

i_clock : external oscillator

i_rx_signal : received RF signal

i_reset : system reset

i_mode : demodulation mode (1 = clock recovery, 0 = standard)

o_word : output parallel data port

o_valid : output data valid

o_led : 7 segment LED output

6.9 e_demod

The e_demod component describes the FSM demodulator. The state diagram for this FSM is included in section 2.2.2. The clock input for this FSM is generated by the e_pulse_gen component. Input is taken from the received signal, and the output consists of the decoded bitstream and a stop signal, which is used to stop the pulse generator (and thus the rest of the receiver) when the FSM demodulator determines that the signal is idle.

The port definition for the e_demod component includes the following signals:

i_clock : external oscillator

i_reset : system reset

i_input : received RF signal

o_output : o_output(1) = decoded output, o_output(0) = stop signal

 

6.10 e_pulse_gen

This component is responsible for generating both sampling pulses for the e_demod component and a bit rate clock for the serial to parallel converter. Both clocks are generated using the standard method, a counter which must count to a defined value before a transition on the clock signal occurs. The counters are reset when the pulse generator receives a stop signal from the demodulator. Thus, each time a new signal starts, the pulses are synchronized with that signal, and the phase relationship between the sampling pulses and the input waveform should be appropriate.

A complete description of this component is included in section 2.2.1.

The port definition for the e_pulse_gen component includes the following signals:

i_osc : external oscillator

o_bitclock : bit rate clock

o_pulse : sampling pulse

i_rx_signal : received RF waveform

i_reset : system reset

i_stop : stop signal (from demodulator)

 

6.11 e_clock_recover

This module describes the clock recovery component. A complete description of this component can be found in section 2.2.3.

The port definition for the e_clock_recover entity includes the following signals:

i_rx_signal : received RF waveform

i_osc : external oscillator

i_reset : system reset

o_bitstream : decoded output

o_bitclock : bit rate clock

 

6.12 e_sp

The e_sp module implements a serial to parallel converter with frame synchronization. The converter reads input bits on the falling edge of the bit rate clock. These are placed in a buffer in the order in which they are received. When a complete 11-bit frame has been received, the first three bits are compared with the expected frame bits. If a match is found, the buffer's contents are latched to the output and the valid signal is pulsed. Otherwise, the data is shifted one position for each new bit received until a match on the frame bits is found.

A complete description of this component can be found in section 2.2.4.

The port definition for the e_sp entity includes the following signals:

i_bitstream : input data bits

i_clk_bit : bit rate clock

i_reset : system reset

o_word : output parallel data word

o_valid : output data valid signal

 

7.0 References

 

Best, Roland E. Phase Locked Loops: Theory, Design and Applications. McGraw-Hill.

Danzer, Paul. The AARL Handbook For Radio Amateurs. AARL.

Filanovsky, Igor M. EE 571 Lab Notes. U of A, 1999.

Forcadas, John and Snip, Anco. EE552 Project: Digital Synthezied Radio Transmitter.

http://www.ee.ualberta.ca/~elliott/ee552/projects/97f/radiotx.html

Grebene, Alan B. Bipolar and MOS Analog Intergrated Circuit Design. Wiley-Interscience.

Kanefsky, Morton. Comunnication Techniques for Digital and Analog Signals. Harper & Row: New York, 1985.

Li, Shum, Wong, and Wong. Dot Matrix LCD Controller and Driver. http://www.ee.ualberta.ca/~elliott/ee552/studentAppNotes/98f/LCD_Driver/app.htm

National Semiconductor. National Operational Amplifiers Data Book. National Semiconductor, 1995. pg 3-46.

Oppenheim, Alan V., and Schafer, Ronald W. Discrete-Time Signal Processing. Prentice-Hall: Englewood Cliffs, 1989.

Peebles, Peyton Z. Jr. Digital Communication Systems. Prentice-Hall: Englewood Cliffs, 1987.

Smith, Jack R. Modern Communication Circuits. McGraw Hill.