library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity tobcd is

port ( bitin:in std_logic_vector(3 downto 0);

BCDout : out std_logic_vector(6 downto 0 ) );

end entity;

architecture b of tobcd is

begin

yo:process

begin

case bitin is

when "0000" =>

BCDout <= "1000000";

when "0001" =>

BCDout <= "1111001";

when "0010" =>

BCDout <= "0100100";

when "0011" =>

BCDout <= "0110000";

when "0100" =>

BCDout <= "0011001";

when "0101" =>

BCDout <= "0010010";

when "0110" =>

BCDout <= "0000010";

when "0111" =>

BCDout <= "1111000";

when "1000" =>

BCDout <= "0000000";

when "1001" =>

BCDout <= "0011000";

when "1010" =>

BCDout <= "0001000";

when "1011" =>

BCDout <= "1000011";

when "1100" =>

BCDout <= "1000110";

when "1101" =>

BCDout <= "0100001";

when "1110" =>

BCDout <= "0000110";

when "1111" =>

BCDout <= "1001110";

when others =>

BCDout <= "UUUUUUU";

end case;

end process;

end architecture;