library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

package test_pkg is

component tobcd is

port ( bitin:in std_logic_vector(3 downto 0);

BCDout : out std_logic_vector(6 downto 0 ) );

end component;

component emitter_block is

port( sp_go, clk : in std_logic;

sp_out : out std_logic );

end component emitter_block;

component emitter is

port( sp1_go, sp2_go, sp3_go, sp4_go, clk : in std_logic;

sp1_out, sp2_out, sp3_out, sp4_out : out std_logic );

end component emitter;

component detector is

port( go, data_ack, rec, clk : in std_logic;

done, timeout : out std_logic;

pos1, pos2 : out std_logic_vector(12 downto 0) );

end component detector;

component pos_alu is

generic ( d_width : positive := 13 );

port ( dumpdata, clk : in std_logic;

data_in : in std_logic_vector( d_width-1 downto 0);

data1, data2, data3 : out std_logic_vector( d_width-1 downto 0) );

end component pos_alu;

component UART2 is

port( clk: in std_logic;

data_rec: out std_logic;

data_ack: in std_logic;

data_in : out std_logic_vector(7 downto 0);

ready_to_send:out std_logic;

data_send:in std_logic;

data_out: in std_logic_vector(7 downto 0);

CTS_comp:out std_logic;

send_req_comp:in std_logic;

data_in_comp:in std_logic_vector(7 downto 0);

ack_comp:in std_logic;

trans_req_comp:out std_logic;

data_out_comp:out std_logic_vector(3 downto 0) );

end component UART2;

component main_controller is

generic( address_width : positive := 5;

datain_width : positive := 6;

dataout_width : positive := 8;

pos_width : positive := 13 );

port( clk : in std_logic; -- Global controls

detected_data, timeout : in std_logic; -- From Detector

posx, posy, posz : in std_logic_vector(pos_width-1 downto 0); -- From Pos Alu

data_in : in std_logic_vector(datain_width-1 downto 0); -- From UART

data_rec, ready_to_send : in std_logic; -- From UART

data_ack, CTS, data_send : out std_logic; -- To UART

data_out : out std_logic_vector(dataout_width-1 downto 0); -- To UART

e_go1, e_go2, e_go3, e_go4 : buffer std_logic; -- To emitter

d_go : out std_logic; -- To detector

mic_address : out std_logic_vector(address_width-1 downto 0); -- To Mic Decoders

data_ack_d, dumpdata : out std_logic;

state_bin : out std_logic_vector(7 downto 0));

end component main_controller;

end package;